Hi, I'm a Ph.D. student at UC Berkeley on the RISC-V team. Happy to answer any questions about the RISC-V ISA or Rocket, our open-source reference implementation.<p>Since there's always confusion about it, I'll start off by clarifying the difference between the two. RISC-V is an open-source ISA standard. Rocket is an implementation of this ISA which also happens to be open source. We do not intend for the ISA to be tied to a single reference implementation. The intention for RISC-V is to enable many different implementations (whether open-source or proprietary). These different implementations can all run an open-source software ecosystem, which currently consists of a GNU toolchain, LLVM, and Linux kernel port.
There's been a fair bit of discussion about this over on reddit:<p><a href="https://www.reddit.com/r/linux/comments/3z9t7k/open_source_processor_core_gains_traction_google/" rel="nofollow">https://www.reddit.com/r/linux/comments/3z9t7k/open_source_p...</a><p><a href="https://www.reddit.com/r/opensource/comments/3z5ue8/open_source_processor_core_gains_traction_google/" rel="nofollow">https://www.reddit.com/r/opensource/comments/3z5ue8/open_sou...</a><p>I'm a cofounder of lowRISC, a not-for-profit working to produce a fully open source SoC implementing the RISC-V ISA, in volume silicon. If you have questions then fire away.
Microsemi (the names "Actel" and "ProASIC" might be better-known) and Lattice are also mentioned as sponsors in the article itself. These are FPGA vendors, which suggests that they might be interested in shipping RISC-V soft cores in their design tools or possibly even shipping chips with RISC-V hard cores (similar to the Xilinx Zynq and Altera SoC families).<p>Notably, Lattice manufactures the only FPGA for which a full open source design flow currently exists (albeit unsupported by Lattice themselves) [1], and has its own set of open source soft processor cores [2] [3].<p>[1] <a href="http://www.clifford.at/icestorm/" rel="nofollow">http://www.clifford.at/icestorm/</a><p>[2] <a href="http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/LatticeMico32.aspx" rel="nofollow">http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/I...</a><p>[3] <a href="http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/IntellectualProperty/IPCore/IPCores02/Mico8.aspx" rel="nofollow">http://www.latticesemi.com/en/Products/DesignSoftwareAndIP/I...</a>
I wonder what Google, HP, and Oracle are planning to do with RISC-V. Will RISC-V-based chips be able to compete with Intel in the server market?<p>Incidentally, I think the first consumer devices to adopt RISC-V will be home wireless routers, because the stock firmwares for those are closed, so they'll just need to be recompiled with a new toolchain. And those devices don't need a GPU.
Has any one created a verification infrastructure with any of RISC-V implementations? The git repository does have a set of tests and benchmarks but could not find any thing more than that.
How does RISC-V compare with the J2 core based on the SuperH architecture by the Open Processor Foundation[1]?<p>1: <a href="http://0pf.org/" rel="nofollow">http://0pf.org/</a>
Can someone explain the advantage of RISC-V vs. other open source architectures (e.g. OpenSPARC?).<p>Are there legal issues that make it more favourable?
I wonder how are they going to compete with Intel?<p>I don’t see how they’re going to match raw performance against those 1tflops+ 20-cores xeons.
I don’t see how they’re going to match performance/watt against 7w quad-core C2338.
I don’t see how they’re going to match price against $20 x5-Z8300.
If none of the above, then why should Google/HP/Oracle/anyone else buy that?