In the networking world Fulcrum built some very low latency switch chips used in switch routers using asynchronous logic. The Alta switch chip was the last of that generation.<p><a href="http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/HC23.19.6-Networking/HC23.19.620-Frame-Pipeline-Davies-Fulcrum-proceedings.pdf" rel="nofollow">http://www.hotchips.org/wp-content/uploads/hc_archives/hc23/...</a><p>Intel acquired Fulcrum and has not had a new product. One can speculate that they were acquired in part for their experience and tool to design asynchronous pipelines.<p>In the DSP world Octasic makes DSPs that use asynchronous desisns:<p><a href="http://www.octasic.com/technology/opus-dsp-architecture" rel="nofollow">http://www.octasic.com/technology/opus-dsp-architecture</a>
>> Imagine what software would be like if subroutines
could start and end only at preset time intervals. “My subroutines all start at 3.68 millisecond intervals; how
often do yours start?”<p>Mine start at 50 microsecond intervals. I've worked on stuff with shorter and longer intervals. Sometimes we have lists of tasks that need to run at different rates, so scheduling becomes a real pain. Welcome to the world of real time embedded software in high performance systems. The same thing applies, we make sure the worst case execution time is within the allowed intervals and use a master clock to sync everything up.
Asynchronous logic is significantly more power efficient, so it may be one approach to "save Moore's Law" (for one generation perhaps). But it would probably require some company that really cares about power efficiency, doesn't care about industry best practices, and is willing to risk hundreds of millions in R&D.
This reminded me of one of Gustafson's reasoning for change in how numerical computations are done - currently used principles of hw architecture result in hw wasting lots of energy and time, mostly in the process where numbers get from RAM to CPU and back. It seems more people already realize this, which is good. I hope to see some general purpose hw inspired by these ideas of efficient computation.
Handshake Technology:
<a href="http://www.ispd.cc/slides/slides_backup/ispd06/8-2.pdf" rel="nofollow">http://www.ispd.cc/slides/slides_backup/ispd06/8-2.pdf</a><p>Warning: Slightly commercial in nature. But some good information about how it works starting on page 4. Worth reading from there.
A few months ago there was another discussion here of an older article of his on the same topic [1].<p>Archive.org has some of their old FLEET architecture papers and slide decks: [2]<p>[1] <a href="https://news.ycombinator.com/item?id=11425533" rel="nofollow">https://news.ycombinator.com/item?id=11425533</a><p>[2] <a href="https://web.archive.org/web/20120227072220/http://fleet.cs.berkeley.edu/" rel="nofollow">https://web.archive.org/web/20120227072220/http://fleet.cs.b...</a>
Hm, I came up with this idea independently, 5 < years < 10 ago, after reading the first third of <i>Code: The Hidden Language of Computer Hardware and Software</i>.<p>Neat!<p>I just figured that you could redesign common ICs so that they had a new wire akin to the "carry" bit. I called it the 'done' wire, and I figured you could just tie it to the CLK of the next IC. Ya know? So 'doneness' would propagate across the surface of the motherboard (or SoC) in different ways depending on the operation it was performing. Rather than the CLK signal, which is broadcast to all points...<p>(I know that my idea is half baked and my description is worse. I'm glad I found this PDF!)<p>I knew the big advantage would be power savings. I called the idea 'slow computing', and I envisioned an 8-bit style machine that would run on solar or a hand crank and be able to pause mid calculation until enough power was available... Just like a old capacitor-based flash camera will be able to flash more frequently when you have fresh batteries in it.<p>You'd just wire the power system up with the logic. Suppose an adder fires a "done" at some other IC. Now, put your power system inline, like MiTM... When it gets the "done", it charges that capacitor (a very small one? :) ) and only when enough power is available does it propagate the "done". ...Maybe the "done" powers the next IC. I dunno.<p>As I said, half baked. Glad to find out that I'm not the only one that dreamed of 'clockless', though!
For those interested in asynchronous circuit design, this group is one of the best in the world in the field.<p><a href="http://www.cs.columbia.edu/async/" rel="nofollow">http://www.cs.columbia.edu/async/</a>
There doesn't seem to be any sign of recent activity on the asynchronous research center site affiliated with the article. Is anyone aware of currently active academic or industrial research groups in this field?
I would personally love try to design some fancy asynchronous stuff, but I got the impression the impression that current FPGAs would make this difficult.
do the ARM Amulet research efforts which came out of Manchester University fall under this? <a href="https://en.wikipedia.org/wiki/AMULET_microprocessor" rel="nofollow">https://en.wikipedia.org/wiki/AMULET_microprocessor</a>