The verilog code had been poorly written. For example, it's not common for a combinational circuit to have an input reset. Latches are inferred in some places that can cause unexpected behavior. That's just my observation though. It's cool to see projects like this. Sadly, it appears to be inactive after seeing the project log.
Another thread with a related subject (and more current projects):<p><a href="https://news.ycombinator.com/item?id=8340283" rel="nofollow">https://news.ycombinator.com/item?id=8340283</a>