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Open-source chip RISC-V to take on closed x86, ARM CPUs

354 pointsby jumpkickhitabout 8 years ago

17 comments

wyldfireabout 8 years ago
I thought that microprocessor production and design was fraught with risk of infringing on other designers&#x27; patents (even for original ISAs). I can see that industry heavyweights have arrived to support RISC-V, so hopefully that comes with a team of professors&#x2F;lawyers that could defend them. But, why now? Why couldn&#x27;t this have happened sooner? Didn&#x27;t Sun try to create an open SPARC processor design? What does RISC-V have that it didn&#x27;t?<p>Is the intent for RISC-V to compete with modern high-end CPU designs, or do we just want to have royalty-free microprocessors for our embedded devices?<p>You might be surprised (at least I was) to learn that peripherals like hard drives and PCI-add-in cards usually have their own CPU executing their own software. Those processors are often MIPS&#x2F;ARM&#x2F;etc based and the manufacturer has to shell out to someone to be able to use that, even if they designed the processor themselves. I can see how this particular market is ripe for something like RISC-V. But does anyone expect RISC-V to really go head-to-head with Xeon, Opteron, ThunderX, Centriq?<p>I sound incredulous because this seems surprising to me, but I have no evidence to suggest whether it&#x27;s as unlikely as I think. I&#x27;ve certainly seen open source software designs far superior to closed source ones, so maybe hardware design is no different?
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filereaperabout 8 years ago
Many people claim to want an open-source chip, but end up balking at its price tag, this is exactly why Raptor Engineering&#x27;s Talos failed. [1]<p>I&#x27;ve pretty much given up hope on a non-x86 based chip hitting our desktops, the closest to reach will be ARM.<p>The economies of scale aren&#x27;t there, I pretty much end up rolling my eyes at each of these articles.<p>[1] <a href="https:&#x2F;&#x2F;www.raptorengineering.com&#x2F;TALOS&#x2F;prerelease.php" rel="nofollow">https:&#x2F;&#x2F;www.raptorengineering.com&#x2F;TALOS&#x2F;prerelease.php</a>
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faragonabout 8 years ago
AFAIK, most advanced RISC-V design includes superscalar and OoOE (e.g. comparable to a MIPS R10000 (1995) or an Intel Pentium Pro (1995)), while the RISC-V for the IoT is comparable to a typical single instructions per clock RISC CPU, e.g. MIPS R3000 (1988).<p>The success in the IoT will depend not only in a cheaper price because of no royalties, but also in the &quot;ecosystem&quot;: peripherals, buses, etc. Running Linux is a huge start, so I have no doubt it can be a success in this field.<p>Regarding the use in mobile and desktop, it will have to wait until SIMD extensions are introduced, and software being adapted (e.g. ffmpeg&#x2F;libav including RISC-V assembly SIMD implementation for the codecs).<p>Anyway, realistically, for the RISC-V getting enough traction, some big player should bet on that, which is currently highly improbable, unless some Apple&#x2F;Samsung&#x2F;Huawei&#x2F;Google gets crazy enough for doing it.
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DonbunEf7about 8 years ago
I want to buy RISC-V, both to play with and to support the cause. What are my options like and should I buy something now or wait for the next generation?
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webaholicabout 8 years ago
RISC-V is atleast 10 years away from competing with x86 and ARM. It is just now getting to a point where it can power arduino class hardware. Long way to go... but looks promising.
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pubbyabout 8 years ago
As someone not knowledgeable about hardware, I really enjoyed reading Agner Fog&#x27;s message board where he and others discuss creating a new open source instruction set: <a href="http:&#x2F;&#x2F;agner.org&#x2F;optimize&#x2F;blog&#x2F;read.php?i=421" rel="nofollow">http:&#x2F;&#x2F;agner.org&#x2F;optimize&#x2F;blog&#x2F;read.php?i=421</a><p>RISC-V is discussed some, and part of the discussion is how to improve it.
blitmapabout 8 years ago
I look forward to a RISC-V proc powering my laptop with some ridiculous Nvidia GPU. We must escape x86 :(
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figersabout 8 years ago
Isn&#x27;t ARM the RISC solution that is already here? Already dominating mobile, Microsoft is soon to be announcing x86 apps running on Windows on ARM
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alkoumpaabout 8 years ago
I wonder how of those fit in a zedboard. (not going to ask how many hours of tool fighting that would require though).
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swedenabout 8 years ago
I see on this thread a lot of people getting blind-folded by the &quot;open-source&quot; term attached to the headline of this article.<p>First of all RISC-V can mean more than one thing: it can refer to the architecture, which is in fact open and free to use, or it can refer to the implementation of the same architecture, which will not be necessarily free or open source. For example, check the so claimed SiFive company which was promising free and open source implementations of RISC-V: <a href="http:&#x2F;&#x2F;www.eetimes.com&#x2F;document.asp?doc_id=1331690" rel="nofollow">http:&#x2F;&#x2F;www.eetimes.com&#x2F;document.asp?doc_id=1331690</a><p>&quot;“A year ago there was quite a debate if people would license a core if there was a free version, [but now] we’ve seen significant demand for customers who don’t want an open-source version but one better documented with a company behind it,” said Jack Kang, vice president of product and business development at SiFive.&quot;<p>By the end of the day, they just decided to follow ARM&#x27;s path by providing license fees to their CPUs.<p>Secondly, when people say that RISC-V is &quot;free&quot; and &quot;open-source&quot; and that will allow companies to create cheaper and more open hardware, that is just an illusion. There are many more things on a SoC other than a CPU (like memories, communication buses, GPUs, power management processors, and so on). Cutting costs on a CPU will not make the cost of an SoC go down to zero, the CPU is just a small part of the puzzle. With RISC-V, you either need to implement the CPU yourself (which will be extremely expensive and time consuming) or you will have to find someone who provides with CPU cores already implemented. And of course that you need to have support and guarantees that the cores you bought will work on silicon. There will be always a huge cost associated when shipping CPUs, you can&#x27;t escape from that.<p>You can already imagine that open-source hardware doesn&#x27;t play by the same rules as open-source software, it&#x27;s a completely different game with completely different rules.<p>And people speak of ARM&#x27;s royalties like if they were a very bad thing. Truth to be told, the royalties you pay ARM can be a very good deal taking into account that you get access to silicon proven CPU cores, support from the best engineers in the industry and you automatically get covered by the many CPU patents that ARM owns. And you can even choose on how you want to pay for ARM&#x27;s CPU licenses: you can either choose to license an already implemented CPU design by ARM or you can buy an architectural license and implement your CPU completely from scratch (this is what Apple and Qualcomm are current doing). You don&#x27;t need to be completely tied to ARM. Even in the royalty fees you can choose whether you want to pay a big upfront license fee but then paying low royalties per device or you can choose to pay a low upfront license but compensating on the royalties per device.<p>There is a lot of misinformation going around the possibilities of RISC-V, mostly of this misinformation coming from people involved in the development of the spec. Don&#x27;t be fooled by the buzzwords &quot;open-source hardware&quot; and &quot;free hardware&quot;.
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psydkabout 8 years ago
After enjoying coding on 680x0 in my youth and later being frustrated by x86, I acclaim that new ISA. There is a design decision I&#x27;m curious about but I could not find related information. How did they come with the names &quot;x0, x1, x2...&quot; for general purpose registers, instead of the more conventional &quot;r0, r1, r2...&quot;?
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posterboyabout 8 years ago
What is so special about reduced ISAs, what&#x27;s the differentiating factors between them?<p>I mean they are so reduced that the ones I&#x27;ve seen are largely the same few logic ops. RAM access and interrupts might differ some, but a) memory access should follow the implementation and b) essentially everything else is memory mapped (avr, c51, pic)
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restalisabout 8 years ago
So many RISC options and almost none for CISC. If you want yet another low power chip, then it makes sense. If, however, you want to get real on efficient cache usage and a high instruction-per-execution ratio, just do yourself a favor and stop ignoring the costly experimenting results that the industry already paid for.
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jbarhamabout 8 years ago
Relevant article: <a href="http:&#x2F;&#x2F;makezine.com&#x2F;2017&#x2F;05&#x2F;03&#x2F;sifive-brings-open-source-to-chip-level&#x2F;" rel="nofollow">http:&#x2F;&#x2F;makezine.com&#x2F;2017&#x2F;05&#x2F;03&#x2F;sifive-brings-open-source-to-...</a>
silurabout 8 years ago
An opensource, non-licensed, low-cost embedded processor -&gt; sifive sells it for 600.000$ minimum.
roryisokabout 8 years ago
I always thought ARM chips <i>were</i> RISC. shows what I know
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jlebrechabout 8 years ago
would there be a advantage to not only creating a reduced instruction set but a minimal instruction set and letting the compiler do the rest. especially when you can add a lot more cores, so that mul becomes a cpu core with a counter and add for example.
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