Eh. None of this is new, and we already anticipated this with LMDB back in 2009.<p>The fact that NVRAM is directly addressable (and thus can bypass the page cache) will eventually play out as irrelevant. It will always be a fact that slower mass-storage will exist, more cheaply than fast in-core storage, persistent or not. The page cache will still be needed even for NVRAM, and the "page" will still be the necessary atomic unit of memory interchange. (Direct access is of course a great thing, but it will be direct access to <i>virtual</i> addresses. Virtual memory, and paging in/out between primary and secondary storage, is never going away. Every commodity system that has tried to do without PMMUs has failed, for numerous good reasons.)<p>The continual allusions to "frequent writes can destroy memory cells" seems to mainly relate to the extremely short lifetime of Intel's 3DXpoint memory, which is from every measure a total failure.<p><a href="http://semiaccurate.com/2017/03/10/intel-mislead-press-xpoint-next-week/" rel="nofollow">http://semiaccurate.com/2017/03/10/intel-mislead-press-xpoin...</a><p>It would be best to ignore 3DXpoint and just focus on STT-MRAM, which is already at parity with DRAM for endurance. (But still lacking in density.)<p>Much of the other stuff in those slides is still off the mark. E.g., LMDB today has perfect crash reliability with zero recovery time. The "write behind logging" they propose still has logging overhead and non-zero crash recovery time - which equals wasted work. Anything that requires logging or any form of compaction or garbage collection is wasted work. It's completely unnecessary, and that has nothing to do with NVM. Treating NVM DB design as if it's an entirely new and different animal is frankly ignorant. The right design works in all scenarios - as LMDB does.
The presentation and the paper pretty much describe how LMDB works already.<p><a href="https://symas.com/lightning-memory-mapped-database/" rel="nofollow">https://symas.com/lightning-memory-mapped-database/</a><p>Except, it allows only a single writer and it's not directly byte-addressable, unless you make a request to preallocate a chunk of fixed-size mmap'ed memory.
I am currently thinking about stating graduate school and this dude "Andy Pavlo" is my hero, the amount of information he pumps (I don't know any other world) to his listeners is outlandish while staying fun and serious and practical at the same time. I watched most of his lectures. I have done some work in industrial reaseach lab with cuda. I did OS a lot and it was my first choice. But after watching his lectures i am seriously considering changing my field to DB. Specially i can do use my Operation Research knowledge in DB much more effective than OS.
"Non Volatile Memory" really means Intel's "3D X-point" memory-- estimated availability of this product for system memory is 2018-ish.<p><a href="http://www.tomshardware.com/news/intel-optane-cascade-lake-dimm,34471.html" rel="nofollow">http://www.tomshardware.com/news/intel-optane-cascade-lake-d...</a>
Video is available <a href="https://www.youtube.com/watch?v=ljrpXVlkQ84" rel="nofollow">https://www.youtube.com/watch?v=ljrpXVlkQ84</a>
anyone knows if a preprint of the paper is available? both the "paper" and the "slides" link point to the same document, i.e. the slides.