> EUV has been waiting in the wings for about 10 years now, always just a few months away from commercial viability. This is the best sign yet that ASML's EUV tech is finally ready for primetime.<p>This is the real message, because creating 5nm chips was already possible[1]. However, creating them massively on scale with the ASML EUV machines is the real challenge.<p>[1] <a href="https://www.semiwiki.com/forum/content/5080-imec-cadence-disclose-5nm-test-chip.html" rel="nofollow">https://www.semiwiki.com/forum/content/5080-imec-cadence-dis...</a>
I wish this wasn't so laughable. What this really shows is that IBM has high margins for their chips, and a long standing tolerance for absurdly low yields and long wafer turn times. That they announce "production" before any of the other fabs is more likely do to PR needs than real technical advancement.
<a href="https://arstechnica.com/gadgets/2015/07/ibm-unveils-industrys-first-7nm-chip-moving-beyond-silicon/" rel="nofollow">https://arstechnica.com/gadgets/2015/07/ibm-unveils-industry...</a><p>EUV has been available for years and no doubt TSMC and SS have their own EUV test chips at 7nm (comparable to Intel 10nm), but the EUV equipment business will be validated by large orders and $ spent, not on prototype silicon. We aren't there yet (but probably will be in a year or so- they've gone from 100W to 150W in the last 9months and need to hit 200-250W).<p>Will we have 1-3nm transistors? Yes.
Will they be commercially viable? Probably No.<p>Moore's law ends when the CFOs decide it's not worth building another multi-$B factory on schedule based on net expected return... which already happened over the last 4 years. Sorry, downvote at will.