Using chip memory more efficiently

For those interested MIT 6.851 Advanced Data Structures covers Cache-Oblivious algorithms if your interested in the general CS&#x2F;Coding techniques to maximize cache usage<p>OpenCourseWare <a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=bY8f4DSkQ6M" rel="nofollow">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=bY8f4DSkQ6M</a>

Take what is fixed and make it flexible.<p>Take what is one and make it many.<p>Take what is repeated and make it one, and fast.

FPGA BlockRAMs have been configurable for the past two decades! The CPU architecture world is borrowing some good ideas from the FPGA architects.

I wonder if projects like openblas can make use of this. Maybe it could be baked into the cpu too somehow.<p>On the other hand, when reading the title I was preparing for a gory Amiga article. In this case it should be on-chip memory or is my non native english fooling me here? But it was at least in the same spirit ;)

I wonder how the OS is supposed to deal with this complexity. It probably needs an API for processes to reconfigure the cache. But then the cache can be private to a process or to a group of processes. Complicated stuff.