Really curious, how can - from a signal processing perspective - 100 applications of a 193 nm wave, come to define 7 nm features? This can't be additive, is there some form of modulation going on on the surface of the silicon? Anyone know?
There are still some pieces that need to come together on this <a href="https://semiengineering.com/issues-and-tradeoffs-for-euv/" rel="nofollow">https://semiengineering.com/issues-and-tradeoffs-for-euv/</a> and <a href="https://semiengineering.com/unsolved-litho-issues-at-7nm/" rel="nofollow">https://semiengineering.com/unsolved-litho-issues-at-7nm/</a>
If TSMC is getting 21E9 transistors on a 12 nm process (i.e. Nvidia Volta), then I assume a 1 nm process would be almost 3E12 transistors. That's insane!<p>Unless power dissipation drops 144x, I can't see that happening, unless it's for memory applications. Crazy to think about though.