Using a 180 nm process, this isn't going to outperform an FPGA at 14 nm either on clock rate or power. And the iteration time will be several weeks instead of minutes. So I'm curious what use cases this will have -- maybe something that doesn't fit into the FPGA mold like asynchronous logic?
Since all circuitry from different projects will be inside a single chip, and all circuits are accessible through the same platform, how do you plan to offer digital privilege access/circuitry protrction to each chip? I mean, random data can be push to jtag (for example) and get results for every circuit embedded inside this chip.
Who cares about performance as long as it works?<p>Pretty sure you're all missing the point.<p>The point is that a kid working fast food during the day and OpenChip/OpenCores enthusiast at night could build whatever they're thinking of over summer vacation.<p>New businesses are no longer started in the garage - they're started in the kitchen.