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Darpa invests $100M in a silicon compiler

415 pointsby adaptevaalmost 7 years ago

22 comments

ur-whalealmost 7 years ago
&quot;Most importantly, we have to change the culture of hardware design. Today, we don’t have open sharing … &quot;<p>This, to the 100th power.<p>The culture in the EDA industry is stuck in the 1950&#x27;s when it comes to collaboration and sharing, it&#x27;s very frustrating for newcomers and people who want to learn the trade.<p>As was pointed out by someone in another hardware related HN thread, what can you expect from an industry that is still stuck calling a component &quot;Intellectual Property&quot;?<p>The un-sharing is built into the very <i>names</i> used to describe things.
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wcrichtonalmost 7 years ago
My advisor at Stanford is working on an open-source hardware toolchain to solve these exact problems. The Agile Hardware Center is trying to bring software methodologies of rapid prototyping and pervasive code sharing&#x2F;reuse to ASICs, CGRAs, and FPGAs: <a href="https:&#x2F;&#x2F;aha.stanford.edu&#x2F;" rel="nofollow">https:&#x2F;&#x2F;aha.stanford.edu&#x2F;</a>
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whaaswijkalmost 7 years ago
I just got back from the Design Automation Conference in San Francisco. It is one of the major EDA conferences. Andreas Olofsson gave a talk about the silicon compiler. There was serious discussion about open source EDA. As far as I could tell it is still unclear what the role of academia will be. It seems tricky to align academic incentives with the implementation, and most importantly, maintenance of an open source EDA stack. However, there is quite some buzz and people are enthused. A first workshop, the &quot;Workshop on Open-Source EDA Technology&quot; (WOSET) has been organized.<p>I also thought I&#x27;d try to answer some questions that I&#x27;ve seen in the comments. Disclaimer: as a lowly PhD student I am only privy to some information. I&#x27;m answering to the best of my knowledge.<p>1) As mentioned by hardwarefriend, synthesis tools are standard in ASIC&#x2F;FPGA design flows. However, chip design currently often still takes a lot of manual work and&#x2F;or stitching together of tools. The main goal of the compiler is to create a push-button solution. Designing a new chip should be as simple as cloning a design from GitHub and calling &quot;make&quot; on the silicon compiler.<p>2) Related to (1). The focus is on automation rather than performance. We are okay with sacrificing performance as long as compiler users don&#x27;t have to deal with individual build steps.<p>3) There should be support for both digital, analog, and mixed-signal designs.<p>4) Rest assured that people are aware of yosys and related tools. In fact, Clifford was present at the event :-) Other (academic) open source EDA tools include the ABC for logic synthesis &amp; verification, the EPFL logic synthesis libraries (disclaimer: co-author), and Rsyn for physicial design. There are many others, I&#x27;m certainly not familiar with all of them. Compiling a library of available open source tools is part of the project.<p>Edit: to be clear, WOSET has been planned, but will be held in November. Submissions are open until August 15.
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adrianmonkalmost 7 years ago
So it costs $500 million every time someone designs a SoC and (before now) nobody has spent $100 million trying to make that more efficient?
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437598735almost 7 years ago
On the opposite side of the spectrum, there&#x27;s Chuck Moore (Forth creator) who in trying to find the simplest combination of software and hardware for his projects devoted a lot of time into a DIY VLSI CAD system. Fascinating history behind it, although the actual OKAD system is essentially trade secret for his company.<p>His site has been down for a while, but someone thankfully mirrored most of the pages here: <a href="https:&#x2F;&#x2F;colorforth.github.io&#x2F;vlsi.html" rel="nofollow">https:&#x2F;&#x2F;colorforth.github.io&#x2F;vlsi.html</a><p>More history about OKAD, plus links to more about Forth both software and hardware: <a href="http:&#x2F;&#x2F;www.ultratechnology.com&#x2F;okad.htm" rel="nofollow">http:&#x2F;&#x2F;www.ultratechnology.com&#x2F;okad.htm</a>
JumpCrisscrossalmost 7 years ago
Side note: when people complain about the military budget, projects like these should be noted. Political reality in America, today, is military R&amp;D and jobs programs are easier to fund than civilian ones; so that’s where projects go to live.
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dalbasalalmost 7 years ago
I have questions, if anyone knows something about hardware. What would a &quot;silicon compiler&quot; let one do? What exactly gets easier&#x2F;cheaper and what exactly could new chip designs yield?
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ThinkBeatalmost 7 years ago
I don&#x27;t quite get the open source angle in the comments here.<p>If I managed to get my grubby hands on a moderately modern computer, I can use all manner of open source software and I can create wonderful new software. The barrier of entry is fairly low in rich countries.<p>If AMD open sourced all the design aspects of their chips, I would have to get a loan to build 100 million fab to have any practical manner to enjoy it?<p>I can see that if Intel&#x2F;AMD&#x2F;NVidia&#x2F;Apple shared all aspects fo their chips cross pollination might bring great things, and academic research would be boosted and might end up giving back more to the community at large, but you are talking about very few entities across the world that can afford fabs.
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esmialmost 7 years ago
What even is this project? There are no details on the DARPA page either.<p>Is it for PCB design, ASIC design or both? Is a constant current source also considered a “small chip” or just digital designs?<p>Basically every EDA tool already has the ability to group sub modules which one could distribute as open source if they chose.<p>Do it in kicad and put your circuit into a hierarchal symbol if you must be all open source.<p>I get hard IP blocks from vendors all the time for inclusion in our ASICs.<p>It’s not the EDA tools that are preventing “openness”.<p>I was just joking the other day how all the PCB designs I’m reviewing lately are just conglomerations of app note circuits and it’s really boring. So to me it seems like there’s plenty of design reuse. :)
zikalmost 7 years ago
I&#x27;m surprised to see no recognition of yosys, arachne-pnr and the icestorm tools which together are a free and open source HDL tool chain which already exists and is pretty widely used.
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alexbeloialmost 7 years ago
A great blog post here (<a href="https:&#x2F;&#x2F;wp.josh.com&#x2F;2017&#x2F;10&#x2F;23&#x2F;adventures-in-autorouting&#x2F;" rel="nofollow">https:&#x2F;&#x2F;wp.josh.com&#x2F;2017&#x2F;10&#x2F;23&#x2F;adventures-in-autorouting&#x2F;</a>) about some different auto-routing software.
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slededitalmost 7 years ago
It should be noted that Andreas Olofsson used to run Adapteva and close to singlehandedly designed the Parallella processor.
kenferryalmost 7 years ago
This kind of spending is so foreign to me.<p>At $250,000 per year per person, that supports 100 people for four years.<p>I… suppose that&#x27;s not completely insane?
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eleitlalmost 7 years ago
Thought I&#x27;ll see Olofsson in there.
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cottonseedalmost 7 years ago
They should have given 1% of it to Clifford Wolf.
tlrobinsonalmost 7 years ago
I wonder if the decline of Moore’s Law will eventually lead to the commotidization of ASIC fabrication?<p>Of course fabricating a chip will never be as cheap as writing a bit of software, but maybe it will eventually be as cheap as, say, injection molding a piece of plastic?
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Aeolus98almost 7 years ago
I might be able to weigh in here.<p>Having these tools as open source and freely available is a huge deal for so many industries. I&#x27;ve worked with these tools at an academic level and now at a startup, and it&#x27;s amazing the magnitude of this enabling technology. Just the tooling investment will be huge, making the core solvers and algorithms more accessible should spawn a whole new wave of startups&#x2F;research in effectivley employing them. Just these days, I&#x27;ve heard of my friends building theorem provers for EVM bytecode to formally check smart contracts to eliminate bugs like these [0].<p>These synthesis tools roughly break down like this:<p>1. Specify your &quot;program&quot;<p>- In EDA tools, your program is specified in Verilog&#x2F;VHDL and turns into a netlist, the actual wiring of the gates together.<p>- In 3D printers, your &quot;program&quot; is the CAD model, which can be represented as a series of piecewise triple integrals<p>- In some robots, your program is the set of goals you&#x27;d like to accomplish<p>In this stage, it&#x27;s representation and user friendliness that is king. CAD programs make intuitive sense, and have the expressive power to be able to describe almost anything. Industrial tools will leverage this high-level representation for a variety of uses, like in the CAD of an airplane, checking if maintenance techs can physically reach every screw, or in EDA providing enough information for simulation of the chip or high-level compilation (Chisel)<p>2. Restructure things until you get to a an NP-complete problem, ideally in the form &quot;Minimize cost subject to some constraints&quot;. The result of this optimization can be used to construct a valid program in a lower-level language.<p>- In EDA, this problem looks like &quot;minimize the silicon die area used and layers used and power used subject to the timing requirements of the original Verilog&quot;, where the low level representation is the physical realization of the chip<p>- In 3D printers it&#x27;s something like &quot;minimize time spent printing subject to it being possible to print with the desired infill&quot;. Support generation and other things can be rolled in to this to make it possible to print.<p>Here, fun pieces of software in this field of optimization are used; Things like Clasp for Answer Set Programming, Gurobi&#x2F;CPLEX for Mixed Integer programming or Linear programs, SMT&#x2F;SAT solvers like Z3 or CVC4 for formal logic proving.<p>A lot of engineering work goes into these solvers, with domain specific extensions driving a lot of progress[1]. We owe a substantial debt to the researchers and industries that have developed solving strategies for these problems, it makes up a significant amount of why we can have nice things, from what frequencies your phone uses [2], to how the NBA decides to schedule basketball games. This is the stuff that really helps to have as public knowledge. The solvers at their base are quite good, but seeding them with the right domain-specific heuristics makes so many classes of real-world problems solvable.<p>3. Extract your solution and generate code<p>- I&#x27;m not sure what this looks like in EDA, my rough guess is a physical layout or mask set with the proper fuckyness to account for the strange effects at that small of a scale.<p>- For 3D printers, this is the emitted G-code<p>- For robots, it&#x27;s a full motion plan that results in all goals being completed in an efficient manner.<p>[0] <a href="https:&#x2F;&#x2F;hackernoon.com&#x2F;what-caused-the-latest-100-million-ethereum-bug-and-a-detection-tool-for-similar-bugs-7b80f8ab7279?gi=e1d1a15e098a" rel="nofollow">https:&#x2F;&#x2F;hackernoon.com&#x2F;what-caused-the-latest-100-million-et...</a><p>[1] <a href="https:&#x2F;&#x2F;slideplayer.com&#x2F;slide&#x2F;11885400&#x2F;" rel="nofollow">https:&#x2F;&#x2F;slideplayer.com&#x2F;slide&#x2F;11885400&#x2F;</a><p>[2] <a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=Xz-jNQnToA0&amp;t=1s" rel="nofollow">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=Xz-jNQnToA0&amp;t=1s</a>
absurdmindalmost 7 years ago
It would be great if they could make something like a Bluespec Verilog[0], but open source. This HDL is far better than traditional ones, IMHO.<p>[0] <a href="https:&#x2F;&#x2F;en.m.wikipedia.org&#x2F;wiki&#x2F;Bluespec" rel="nofollow">https:&#x2F;&#x2F;en.m.wikipedia.org&#x2F;wiki&#x2F;Bluespec</a>
baybal2almost 7 years ago
I don&#x27;t see how this is not literally the same thing any HDL synthesis program does. How?
petraalmost 7 years ago
I see many chip vendors on the list of participating companies.<p>Won&#x27;t this project reduce barriers to entry for their industry ? and if so, isn&#x27;t it against their interests to participate?
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Havocalmost 7 years ago
I thought chips are already largely algo designed?
spencerg12almost 7 years ago
nice