First of all, kudos to WD. This makes me feel good about spending $1500 on their spinning drives just last week.<p>But on a more practical note, what kind of board and toolchain does one need to get this going on an FPGA? Is there a readme somewhere that would walk one through the process?
They have an open-source software simulator for this as well: <a href="https://github.com/westerndigitalcorporation/swerv-ISS" rel="nofollow">https://github.com/westerndigitalcorporation/swerv-ISS</a><p>I'm curious how the performance compares to other open-source cores
How does it compare to BOOM [1], both RISC-V and both open source.<p>[1] <a href="https://github.com/riscv-boom/riscv-boom" rel="nofollow">https://github.com/riscv-boom/riscv-boom</a><p>Edit: Not sure why I am getting downvoted, isn't this a valid question?
It would be their dream come true if the hw oss community (very small) takes this up and develops it into something huge like for sw projects. There is so much manpower needed to develop these kinds of things - what better way than oss.<p>However, too little, too late, ee industry. An entire generation of top tier college students have pretty much skipped ee.
Would have been awesome if they joined the effort of developing FIRRTL[1][2] and using it as a universal (LLVM-alike) hardware intermediate language, better suited modern chip design needs than Verilog or VHDL[3].<p>[1] <a href="https://github.com/freechipsproject/FIRRTL" rel="nofollow">https://github.com/freechipsproject/FIRRTL</a><p>[2] <a href="https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/11/Reusability-is-FIRRTL-Ground-Izraelevitz.pdf" rel="nofollow">https://aspire.eecs.berkeley.edu/wp/wp-content/uploads/2017/...</a><p>[3] <a href="https://github.com/SymbiFlow/ideas/issues/19" rel="nofollow">https://github.com/SymbiFlow/ideas/issues/19</a>
I've been meaning to get started with RISC-V for some time now but can't find much on it for total beginners online. Can anyone recommend a starting point for a total noob?
So this is the logic of the controller in Verilog. But I don't see any test scripts. I am not an expert in logic design, but it seems to me that validation is at least as expensive and time consuming as the actual creation because you cannot afford mistakes in the ASIC masks. Am I missing something here?
Great work, many thanks to WD. As far as I see only a subset of the SystemVerilog features is used. Is there a "coding standard" somewhere available specifying this subset with a rationale? Is it mostly to be compatible with Verilator? Is there information available why they used Verilator and how it has proven itself?
Can someone explain a bit what’s happening around the division?
<a href="https://github.com/westerndigitalcorporation/swerv_eh1/blob/master/design/exu/exu_div_ctl.sv" rel="nofollow">https://github.com/westerndigitalcorporation/swerv_eh1/blob/...</a><p>Or give me some google keywords? Is there a link with the pentium bug?
Wester Digital if you are reading this!<p>Pleeeeze I want to have access as an end user. I'd like to do a predicate push down and be able to write into the DRAM buffer and the flush a commit. Or pin certain blocks directly into DRAM. Pleeeeze!