Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput?<p>There is obviously a market for this as both giants are building platforms.
>why the AMD EPYC “Rome” generation will <i>likely</i> see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function.<p>Emphasis mine. This seems to be pure speculation, not 'news'.
Just added a quick note. Everyone in the industry that contacted me today about this seems to be calling it WAFL or something that sounds like "Waffle" for the extra bonus PCIe lanes.