Up until around 2012, realworldtech.com and anandtech.com used to publish rather more detailed descriptions of the microarchitecture inside each core.<p>Is anyone publishing things like that these days? I mean pages like these:<p><a href="https://www.realworldtech.com/haswell-cpu/4/" rel="nofollow">https://www.realworldtech.com/haswell-cpu/4/</a>
<a href="https://www.anandtech.com/show/6355/intels-haswell-architecture/8" rel="nofollow">https://www.anandtech.com/show/6355/intels-haswell-architect...</a><p>(I noticed that Agner Fog's chapter on Ryzen is conspicuously missing a "Literature" section.)
There must be a simulation for this kind of architectures to see what is the best combination of size and components while making it practical! I wonder if anyone knows something like that? A tool to minmax these choices and estimate if this can be done with resources they have got.
> “We like features that improve both power and performance,” Clark elaborated. “Being on the right path more often is important because the worst use of power is executing instructions that you are just going to throw away. We are not throwing work away after we figure out dynamically that we were wrong to do it. This definitely burns more power on the front end, but it pays dividends on the back end.”<p>Every documentation I've seen is quite light on the branch prediction improvements. Going by the slides, they improved is accuracy by 1/3; I'd be curious to know how.
Side note: if your superscalar is big enough (yeah, those registers use power), couldn't you just get rid of branch prediction at no performance cost (doing something else while waiting for the data)?<p>My only grudge against Zen (as a consumer) is that the AM4 socket is intended for both APUs and CPUs. While this is a good thing, I have a couple utterly useless video outputs on my motherboard. I would have liked AMD to include some display driver circuitry on every chip. Maybe in the I/O die, if they use such a thing in all of their designs going forward? I mean, I would be quite content with using software rendering when I need to drive a screen, or even spare a bit of memory bandwidth and CPU cycles to drive an extra display from my desktop's graphics card.
This didn't really seem like a deep dive compared to the anandtech article. I was hoping for some memory bandwidth benchmarks, since this should be the first chip that has 8 channels without caveats (looking at you power 9). It's also not clear if it's 16 channels with 2S, but I suspect not.<p>Edit: the picture from AMD in this review makes me think it can hit 16 memory channels with the two socket version. Does anyone know if this is true?
The poster is holding a line of bash to the standard of code and is illustrating that readability should be the goal and a way of bringing bash commands to a standard of readability for something like a PR. Readability is really there to show _intent_<p>I would say though that if you are bringing this to the code standards of today then this should really be wrapped up in some kind of unit test (<a href="https://github.com/sstephenson/bats" rel="nofollow">https://github.com/sstephenson/bats</a> )for it to pass the PR. That would make the code a bit more maintainable and can be integrated as a stage in your CI/CD pipeline.<p>If we do that then the intent would be clarified by the input and the expected output of the test. Then then the code would at least be maintainable and the readability problem becomes less of an issue when it comes to technical debt.<p>I've done this plenty of times with my teams and its certainly helped.