5 and 10 year plans are <i>always</i> over optimistic projections by people who can't deliver in the present to reassure investors faith.<p>They might ship 1.4nm, but it has a good chance of having Soviet tractor quality.
I know that past performance does not indicate future results but looking at their 2013-2016 roadmap [1] which promises 10nm at Q1 2016 (which never happened!), I strongly doubt their future roadmap will hold.<p>[1] <a href="https://wccftech.com/intel-processor-roadmap-leaked-10nm-cannonlake-skylakee-arrives-q3-2016-skylake-muy-chips-q4-2015/" rel="nofollow">https://wccftech.com/intel-processor-roadmap-leaked-10nm-can...</a>
So if Intel actually stayed on track for this roadmap, they're saying "we only have 10 years left to advance our fabs". Unless 1.4nm is actually meaningless, they'd be edging up to electron tunneling issues with a contacted gate pitch of ~10 atoms across.<p>I'm being optimistic with this guesswork. Intel's historical naming is that cpp = 3-5x node name [1]. Silicon lattice spacing is ~0.54nm.<p>[1] <a href="https://en.wikichip.org/wiki/intel/process" rel="nofollow">https://en.wikichip.org/wiki/intel/process</a>
I really liked the last quote:<p>> It’s worth also pointing out, based on the title of this slide, that Intel still believes in Moore’s Law.<p>> Just don’t ask how much it’ll cost.<p>I once got an opportunity to ask something similar to an Apple executive during a presentation on their hardware capabilities (it was a university event).<p>He laughed and answered another part of my question.
A poorly held secret in the semi industry is that transistors have stopped scaling at around 30nm - the practical limit of 193nm litho.<p>What has been scaling was the amount of free space in between them, metal layers, design rules, cell designs and such.<p>Before transistor scaling stalled, any process node shrink was an automatic performance gain without any side effects, but not so much after. Some designs may well be seeing net losses with process shrinks these days.<p>From 10nm on, higher density is actually hurting your performance, not adding it. For a process technologist, you have now to work on both performance, and density in parallel, and not solely on the last one thinking that gains in it will automatically translate into gains in performance.<p>So its a tricky business now to both squeeze more transistors into a design, and have a net gain from it.
Just as an interesting aside does anyone have a list of weird engineering hacks used in these processes to get smaller and smaller transistor densities? There must be some very clever stuff to jam them in there and still be able to etch the lines.
You can always count on Intel's marketing team for top notch slide presentations.<p>However, Intel is closer to 22nm than 7nm let alone anything smaller than that. ( I'm talking about consistent product lines that anyone can buy at a store ), not some Houdini show.<p>On the commercial side they have a huge footing and large tentacles so they don't need to worry too much about time-frames, let's hope they also don't worry too little..
For comparison, Intel's roadmap from IDF2013: <a href="https://files.catbox.moe/psgnbp.jpg" rel="nofollow">https://files.catbox.moe/psgnbp.jpg</a>
What kind material science improvement would make non-marketing, real ~10nm scales a reality? I literally have no idea how RnD works in this field. Is it trial and error? How do these scientists come up with ideas that increases the transistor density? Do our current gen CPUs have 2d or 3d curcuit layout? How one can learn about these stuff without working in the field?
Adding to my previous post, a lot of people don't understand where 10nm EUV litho stands in the grand plan of thins.<p>"If EUV doesn't make a more performant chip, what it does?" EUV is there to alleviate <i>extreme</i> process costs associated with multiple patterning, and process cycle time.<p>Even if EUV tool does 1 exposure a little bit slower than quadruple patterning, it can do 4 patterning steps in one — a very huge thing in process technology.<p>You have then lessen the amount of thermal processes performed on the device. You may have more defects, but on overall higher quality, higher performance devices in the end.
> Intel expects to be on 2 year cadence with its manufacturing process node technology, starting with 10nm in 2019 and moving to 7nm EUV in 2021<p>Not to say it could <i>never</i> happen, but given how many years Intel has spent on 10nm with it always been 'next year' tech year after year, 7nm in 2021 seems overly optimistic for me.<p>I guess time will tell if they got it right this time.
The "backporting" doctrine clearly implies total lack of faith in process roadmaps, to the point of compromising processor designs and increasing cost and time to market to avoid committing to a millstone around the neck.
All change requires energy, and we're going to have less energy, so the speed of change inevitably has to go down.<p>Because the only energy added to the planet comes from the sun and the only viable option to collect that energy are trees and plants.<p>(I'm going to post this comment on every naive technology optimist post, you can downvote me all you want, I have to do this to be able to sleep at night, fake karma is not more valuable than real karma)
What perplexes me is that neither Intel, AMD, IBM, or any other company, as far as I can tell, is pursuing the bootstrapping path of self-assembling nanotech. Once someone does it, every other company is going to be left several orders of magnitude in the dust, so it surprises me that no one is going for it.