Also newsworthy: Lattice drops recent EULA clause forbidding fpga bitstream reverse engineering <a href="https://hackaday.com/2020/06/06/lattice-drops-eula-clause-forbidding-fpga-bitstream-reverse-engineering/" rel="nofollow">https://hackaday.com/2020/06/06/lattice-drops-eula-clause-fo...</a> therefore 2020 could be a milestone for open FPGA toolchains!
Is there any published rationale for the RISC-V instruction encoding?<p>A few months back I set out to write a software emulator of RISC-V for fun. I expected the instruction set encoding to lend itself well to a very simple implementation, eg. something you could decode in 5-10 lines of C plus some tables.<p>But the instruction encoding is much more irregular than I expected: <a href="https://github.com/ucb-bar/riscv-sodor/blob/master/src/common/instructions.scala" rel="nofollow">https://github.com/ucb-bar/riscv-sodor/blob/master/src/commo...</a><p>In particular:<p><pre><code> - The bit patterns allocated to the simplest instructions
(eg. rv32i) seem random. Why not allocate starting from zero
to allow dense jump tables?
- I can't make any sense of the groupings. A bunch of instructions
have 0b1100011 in the lowest bits, do these instructions have
something in common?
</code></pre>
I assume there is some rhyme and reason to all this? Where is this explained?
The ULX3S is great! I built myself an early prototype a year ago, and have used it every so often for occasional hacks. It has since evolved to be a first-class citizen in a number of projects and frameworks (LiteX, including LiteDRAM), which makes it great to get started with.<p>Also worth noting, that you can use a fully open source flow (Yoys + nextpnr + prjtrellis) for this FPGA family. Here's a repository I made that shows a basic blinky for an ULX3S: <a href="https://github.com/q3k/ulx3s-foss-blinky/" rel="nofollow">https://github.com/q3k/ulx3s-foss-blinky/</a>
Where's the article? I see mostly a bunch of loosely related bullet points.<p>Edit: After a lot of back and forth, perhaps this is a good intro: <a href="https://hackaday.com/2019/01/14/ulx3s-an-open-source-lattice-ecp5-fpga-pcb/" rel="nofollow">https://hackaday.com/2019/01/14/ulx3s-an-open-source-lattice...</a>
Remember there is a lecture by a guy who demo on a game emulation program. Wait for it since.<p>Just placed an order : <a href="https://www.crowdsupply.com/radiona/ulx3s" rel="nofollow">https://www.crowdsupply.com/radiona/ulx3s</a>
Can anyone comment on how this compares to the popular Terasic DE10-Nano used for the MiSTer project? The price point is around the same and I see they note running video game cores as a market for this device, but I have absolutely no clue how to reasonably compare FPGAs.<p>From my rudimentary understanding it looks like this doesn't have a hard CPU and has a smaller FPGA, so I'm guessing we have a fair bit of "open hardware tax" at play here too.
2x more resources compared to $30 <a href="https://github.com/q3k/chubby75" rel="nofollow">https://github.com/q3k/chubby75</a> at 5x the price