I did an analysis of this PoW at my line of work and I would say that it is really complicated. Unnecessarily so, I have to add.<p>I also have a comment about ASIC resistance.<p>There are tools that allow to customize hardware upon programs it will execute, [1] is an example of one such tool, there are some others.<p>[1] <a href="http://openasip.org/tta.html" rel="nofollow">http://openasip.org/tta.html</a><p>If you write a RandomX code generator and interpreter and customize the CPU hardware using tools like one above you will get an optimized version of the hardware. Take a look at [2] for a results of such codesign attempts for Fourier transform. The optimization in energy efficiency can be as high as 100+ times over general purpose processors and on par and exceeding ASIC implementation.<p>[2] <a href="https://www.researchgate.net/publication/321700396_Codesign_case_study_on_transport-triggered_architectures" rel="nofollow">https://www.researchgate.net/publication/321700396_Codesign_...</a><p>One would duly note that RandomX employs floating point instructions in some parts of hashing process. I will respond that floating point operations can be expressed as operations on fixed point values and these hardware parts can (and will) be shared with other computations. Basically, the codesign tool will implement for you a split (FP)ALU. This will also increase energy efficiency over GPU and general purpose CPUs which have different paths for FP and integer computations and usually do not share ALU parts between these.<p>To comclude, first, RandomX is needlessly complicated. Second, I think that ASIC version can be attained without writing everything in Verilog by hand, you may stick with C reference implementation for most of the work. And, last but not least, the gain in hashes per joule from ASIC implementation can be much higher than 2-5 times over CPU or GPU.
This PoW is rather complex and takes nontrivial amounts of time and memory to verify. It accepts these downsides in an attempt to achieve "ASIC resistance", which means limiting the potential efficiency gains of custom chips to a small factor like 2x or 3x. This should make their design and manufacture economically unattractive, with long ROI times. And thus allow commodity hardware to remain competitive.
We should reject PoW algorithms as generally destructive. When I say destructive, I mean they cause more global harm than they purport to alleviate.<p>PoW should have been set aside as soon as it was generally understood that the network's energy consumption might be unbounded.
Someone should make a PoW algorithm based on useful things like game theory; for example a chess bot competing against other chess bots, the top winner forges the block and gets the rewards. This is still not extremely useful, but better than just hashing useless strings.<p>Ideally, PoW algorithms should be focused on real science and/or economic problems.
Total sidenote but someone should start a cryptocurrency that is proof of Storage-space(does that exist?), where you have to allocate space to mirror the content of the Internet Archive. Is there a way that could work? (I know almost nothing about cryptocurrency)