The lecturers are from the same team developing Low Level Hardware Description (LLHD) language:<p><a href="https://github.com/fabianschuiki/llhd" rel="nofollow">https://github.com/fabianschuiki/llhd</a><p>p/s: It seems that Lecture 7 slide is missing, though.
If you want a great introduction to, and appreciation of, SoCs — given the announcements yesterday and to understand what goes into something like the M1 a little better.
That's a very good lectures!<p>However, there is one thing is regrettable to me in lectures that talks about the micro-architecture of superscalar processors: they never talk about the register bank micro-architecture. The focus is always on the micro-architecture of the compute units.<p>Knowing that the wire area of a conventional register bank grows by the square of the number of read/write ports, and that superscalar processors require an increasing number of read/write ports, the micro-architecture of the register bank quickly becomes critical with the number of issue.<p>But there is very little information on the right micro-architectural strategy in this regard.
There is some information on GPU register banks, but very little about modern CPU designs.