Reading about separate row and column addresses reminded me that the Apple II had its address lines arranged in such a way that the video circuitry would naturally read every row of memory, thus obviating the need for a separate refresh circuit.<p>(To RAM, the order of address lines doesn't matter)
I remember those chips as they were the ones in the ZX81 16K RAM Pack. 8 of the little beauties.<p>The RAM Pack itself was a nightmare. If it wobbled the computer would crash. I held mine on with blu-tack - lots of it. Every now and again I'd have to take it off and clean the contacts by rubbing the oxide layer off with an India rubber. It used to run quite hot too.<p>Despite the problems, the RAM pack was the best upgrade I had!
Cut my teeth on this device. I remember the excitement at getting the first 4164 samples: Single 5V rail: luxury. Had to invent bank switching to use more than 8 of them:) Good times.
At some level, all signals are analog. Lovely clever tricks every step of the way are necessary to make the nice abstract digital levels we try to think about. How might such tricks discriminate more states? can we have 3, 8, more state "bits"?
Nice. This is a really interesting design.<p>I tend to like NMOS because of its compactness and simplicity (disadvantage is usually dissipating static power of course.)
Love the articles. I definitely want to spend a bit more time with it. The section on the sense amp was great.<p>But one thing I was left wondering was how was the refresh managed?<p>Was it just the act the reading/writing had the side effect of refreshing? Therefore the memory controller had to keep track of when & what was accessed?