It looks like you're using an ice40 FPGA?<p>If you can make your project work with 38 I/O pins you could probably get it fabricated in ASIC by Efabless free. You just need to meet their repository requirements and make your verilog module conform to this interface:
<a href="https://github.com/efabless/caravel/blob/master/verilog/rtl/user_proj_example.v" rel="nofollow">https://github.com/efabless/caravel/blob/master/verilog/rtl/...</a><p>The openlane tool converts your verilog all the way down to final ASIC design...<p>You'd need to license everything Apache 2.0 though. And it would have to be done soon, the deadline is Nov 30th.
This looks very good well done! Microsoft need to hire you for the team asap!<p>It always cracks me up playing minecraft on xbox one x and once your village hits few hundred villagers framerate (when running beta from insider it's shown on screen) drops to like 3-4fps