Why is this interesting? Rosetta 2 is documented to not support AVX: <a href="https://developer.apple.com/documentation/apple_silicon/about_the_rosetta_translation_environment" rel="nofollow">https://developer.apple.com/documentation/apple_silicon/abou...</a>
Is there any long-form documentation (specifically an optimization manual) for M1 yet?.<p>Currently the only details I can find about the microarchitecture is either press waffle or things reverse engineered via timing (you can look for bumps in graphs to find the widths of various speculative features of the CPU).<p>It would be very Apple not to publish any (Fucking sad if true)<p>Edit: Intel, like them or not, have genuinely very good documentation (Much better than AMD's) and seem to have really thought about actually <i>using</i> their performance - AMD can really deliver the goods on their terms, but they still lag behind in both software (particular compared to Nvidia) and documentation (Intel's optimization manual is 850 pages; AMD's is 45 pages). AMD basically give you a raw list of RDPMC event assignments to play with, Intel actually tell you how to use them.
TL;DR: A change was made to set the minimum CPU level (instruction set target) for Big Sur builds to Ivy Bridge. This assumes the presence of AVX instructions on all Big Sur machines, which is true for Intel macs. Rosetta is a Big Sur "machine" that does not support AVX. Therefore, the assumption was false.
why doesn't rosetta support avx? arm has neon and sve... i would assume that there's equivalence for most basic vector math instructions and for those that there isn't, like the weird sha256 and aes instructions, they could just be emulated in software?