An Open-Source FPGA-Optimized Out-of-Order RISC-V Soft Processor (2019) [pdf]

To push this up from the comments, if you&#x27;re interested in why this is important or what the authors are trying to do the PDF where they describe their approach and architecture is really interesting.<p><a href="http:&#x2F;&#x2F;www.rsg.ci.i.u-tokyo.ac.jp&#x2F;members&#x2F;shioya&#x2F;pdfs&#x2F;Mashimo-FPT&#x27;19.pdf" rel="nofollow">http:&#x2F;&#x2F;www.rsg.ci.i.u-tokyo.ac.jp&#x2F;members&#x2F;shioya&#x2F;pdfs&#x2F;Mashim...</a>

Is there a quantification of &quot;high performance&quot;?<p>It will obviously be much lower than the IPC of an actual high performance CPU (modern x86-64), but how big is the difference? And how does it compare to typical mobile processors?

I am glad they are using System Verilog. It is hard for me to understand why SiFive chose Chisel as RTL language. I think that quietly slows down the RISC-V adoption. I honestly tried to understand the advantages of Chisel, but I can not see any. There is an answer on Stack Overflow regarding Chisel benefits, it is just embarrassing [1].<p>[1] <a href="https:&#x2F;&#x2F;stackoverflow.com&#x2F;questions&#x2F;53007782&#x2F;what-benefits-does-chisel-offer-over-classic-hardware-description-languages" rel="nofollow">https:&#x2F;&#x2F;stackoverflow.com&#x2F;questions&#x2F;53007782&#x2F;what-benefits-d...</a>

The gif of the Konata pipeline visualizer seems to show pretty much one instruction per cycle most of the time... Many parts of the trace show as low as 0.2 instructions&#x2F;cycle..<p>Wouldn&#x27;t we expect much higher numbers (more parallelism) considering the number of frontend&#x2F;backend pipelines?

All those abbreviations on the block diagram make it very difficult to interpret. A key map in the image would be great, or at least some markdown directly below it.

For people in the industry: how likely are we to get RISC-V servers&#x2F;VMs&#x2F;laptops&#x2F;desktops in the next 5-10 years? You know, go on a PC Part Picker and assemble a RISC-V desktop, for example.

Well done to the authors for making a surprisingly readable core for once.

I guess somebody will implement 64 bit GC extensions to run linux on it.

I know Yosys has a limited support for System Verilog, but any success synthesizing this using FOSS toolchain ? What features are missing if not successful ?

Is anyone working on low power open risc-v implementations? (Ideally including manufacturing, i.e. a physical device that I could buy&#x2F;build on top of)

If the FPGA is a closed-design are we really that better off?