>"The pixel clock frequency can be synthesized from the 27MHz oscillator built into the labkits by using one of the twelve Digital Clock Managers (DCMs) built into the labkit FPGA. DCMs have numerous uses, one of which is generating a clock signal whose frequency is some multiple of the frequency of a reference clock."<p>Related: <a href="https://www.xilinx.com/products/intellectual-property/dcm_module.html" rel="nofollow">https://www.xilinx.com/products/intellectual-property/dcm_mo...</a><p>>"The Digital Clock Manager (DCM) primitive in Xilinx FPGA parts is used to implement delay locked loop, digital frequency synthesizer, digital phase shifter, or a digital spread spectrum. The digital clock manager module is a wrapper around the DCM primitive which allows it to be used in the EDK tool suite."<p>[...]<p>>"Device Family: Virtex-4, Virtex-II Pro, Virtex-II, Spartan-3"<p><a href="https://en.wikipedia.org/wiki/Digital_clock_manager" rel="nofollow">https://en.wikipedia.org/wiki/Digital_clock_manager</a><p>>A digital clock manager (DCM) is an electronic component available on some field-programmable gate arrays (FPGAs) (notably ones produced by Xilinx). A digital clock manager is useful for manipulating clock signals inside the FPGA, and to avoid clock skew which would introduce errors in the circuit.<p>Uses<p>Digital clock managers have the following applications:[1]<p>o Multiplying or dividing an incoming clock (which can come from outside the FPGA or from a Digital Frequency Synthesizer [DFS][citation needed]).<p>o Making sure the clock has a steady duty cycle.<p>o Adding a phase shift with the additional use of a delay-locked loop.
o Eliminating clock skew within an FPGA design.<p>See also:<p>Phase-locked loop"