Forth SoC Written in VHDL

I wonder if this would fit in a Lattice ICE40 FPGA so that Xilinx ISE could be avoided (very buggy) and open source tools like Yosys could be used instead.

Looks interesting, it is known that J1 is very tiny, how many can fit in the Spartan-6 XC6LX16 mentioned, do you have plan of create a multi-core system with this?

I&#x27;ve been considering attempting something like this with Verilator output which is mixed into a GUI produced by QT.<p>This is truly awesome. I can&#x27;t wait to play with it!

Can this run on a VDHL simulator?

Silly idea, is there any Lisp SoC, like the famed Lisp machines?