Gone over sections 16..19 - Several questions are clearly nonsense, eg 17.11) "MISR the BIST out of Z!Xussia" or vague eg 16.4b) "Explain at least 2 different types of data Perl/Python can handle". Question 18.h) "33-Dimensional Maze Router" is more of a strange fever dream than an actual question<p>Section 17 is mostly testing for rote learning, I'm guessing these questions are taken from some university course?<p>My favourite quesiton is 18.a) "Verilog Syntax/compile errors" which asks you to spot all the mistakes (while ignoring behaviour) and hint at a fix -- but since you're allowed to ignore all behaviour a valid (and reasonable) fix is actually to delete it all.<p>Beyond these superficial issues I'm mostly interested because my company takes in a lot of EE graduates for beginner FPGA roles, and in our experience almost all undergraduate instructive material is 30 years out of date. Almost all graduates still seem to get taught that VLSI design is done by manually instantiating combinatorial gates and D type flip flops.<p>And in honesty, I think this document falls into the same trap, section 18 asks the learner to design a transparent latch as a single module. It's very rare to want put a transparent latch in an FPGA, and you'd never dedicate an entire entity to describing one. It also asks for an 8-to-1 mux, a 4 bit shift register, and a 16 bit shift register.<p>However I think question 18.f) "FSM – Verilog Design of a Crosswalk Controller" is actually a very good example of the right sort of question (for, say midrange/advanced beginner), which will focus the students' attention on "normal" RTL design. Specifically I like that is requires specific clock timings (assert X for 32 clock cycles, assert Y for 10 cycles), as I think off-by-one timing errors in FSMs are a very common problem for beginners.<p>A more difficult extension (perhaps a part of student's first introduction to concurrency in an FPGA) would be to design a crosswalk controller with slightly more complexity.. maybe multiple buttons or multiple junctions or whatever.
These are good for undergrad CompE or EE students for practicing before an exam, but irrelevant for industry hardware people.<p>You'll be asked to draw a low-side drive with a MOSFET and an inductive load, given a circuit to analyze and find bugs, etc. Asked basic stuff. Ohm's Law, Smith chart if RF. No trivia like this.
Disagree with the answer to the first question on sizing. Resistive model doesn't seem appropriate for CMOS transition, the MOSFET will spend most of the time in saturation, so you don't need to upsizes gates just because they're in series. (The real answer in a modern process node is that parasitics dominate, and you need to simulate the design with the extracted parasitics from the layout. But I get that it's just an academic exercise.)
Pretty good collection of questions. A bit weird with the the huge, hand drawn figures here and there in the questions section. Sometimes they seem to be illustrations, sometimes a partial solution.<p>Cool to see time borrowing included in the material.<p>One thing I jumped on was the questions related to Verilog. This document is (c) 2021, but uses module declarations, syntax etc from Verilog pre 2001 (1995-ish). OTOH it actually teaches building FSMs with two processes, which is good to see.<p>Also, there are quite a few minor errors in the material. Spelling etc. But overall a good set of digital electronics and VLSI questions.
Why is the download section so small and in the corner of the page on arXiv.org desktop version and not in the main section under the title and preface/intro like on mobile?
You can read and see "Software Engineer" literally everywhere nowadays; It feels very strange to see "Hardware Engineer" in the title.
Ah yes, because "hardware engineer" means "digital ASIC designer" now, and "practice problem" means "pile of barely edited context-free questions without any explanation".