StarFive Dubhe 64-bit RISC-V core to be found in 12nm, 2 GHz processors

This will be the first RISC-V chip I have heard of that implements the popcount instruction.<p>To my knowledge it is not required in any standard profile, so getting a compiler to generate the instruction will be messy.<p>When run on a chip that does not support the instruction, typical 10x optimizations become 10x pessimizations instead.

Will we see the rise of Libc shims soon like those for JavaScript? RISC V feature support looks notoriously fragmented.

Are the vector ops variable width? And 1024 bit?<p>The RISC-V standard is quite expansive, I can&#x27;t tell the intent in the article.

GlobalFoundries could be a big player in this market segment. Their lithography tech isn’t bad at all.