The RP2040's PIO is awesome. Here are two retro-related projects I did in the last ~year.<p>You can capture video in a weird format with PIO on one core, and output it with PIO (in a standard format like VGA, or even DVI) on the other core, like here: <a href="https://blog.qiqitori.com/2022/09/raspberry-pi-pico-15-6-khz-analog-rgb-to-vga-adapter-part-1-poc-wip/" rel="nofollow">https://blog.qiqitori.com/2022/09/raspberry-pi-pico-15-6-khz...</a><p>Or you can implement old DACs that expect a weird input data format, to a certain extent, like here: <a href="https://blog.qiqitori.com/2023/03/raspberry-pi-pico-implementation-of-the-ym3012-dac-mono/" rel="nofollow">https://blog.qiqitori.com/2023/03/raspberry-pi-pico-implemen...</a><p>(Now I'm almost at the end of my sabbatical but think these projects (and others) were totally worth doing even if it meant living off savings, heh.)
As soon as I read about the programmable I/O setup, it reminded me of the Propeller series chips from Parallax. The "cogs" that are the main processors of those chips aren't as general use as something like the STM32 cores, but they do certain things very, very well.
That's interesting!<p>If AMD incorporates scaled down Xilinx's FPGAs into their x86-family product line, that could bring a lot of RasperryPi's community effort into a mainstream products too (home PC) and let us experiment embedded software directly on our PC! ...and break our main PC during our experiments too, oopsie. But it would be worth it haha.
I stumbled upon this project a few weeks ago, while starting to get a better handle on how to use PIO (and the rest of the RP2040 infrastructure, like PIO/DMA interactions). I searched for it at first, thinking that an HDL implementation of PIO would be a good way to test and simulate PIO interactions and timings. It turns out there are some neat and more specific PIO simulator/emulator projects out there, so I've moved that way.<p>Still, this project is quite interesting. I have a design I'm working on that would really benefit from 4 PIO blocks all cooperating on a piece of RP silicon. Since that's not likely to ship anytime soon, I am vaguely interested in piecing together some HDL that stitches together a RISC-V core with several PIOs.
that's very cool, maybe one day it can be burnt into a CPLD or integrated into other MCUs' designs directly.<p>Motorola used to have CPM, TI has PRU for higher end chips.<p>All of these are doing similar things: using software to create IO peripherals on the fly.