"...this is interesting is because POWER9 is basically the first time the public got a real view of how sophisticated the backstage cast actually is of a modern server CPU."<p>Not quite correct; the OpenSPARC T1 and T2 were publicly released and available by 2008.<p><a href="https://www.oracle.com/servers/technologies/opensparc.html" rel="nofollow">https://www.oracle.com/servers/technologies/opensparc.html</a><p>"Large parts of this process are handled by vendor-supplied mystery firmware blobs, which may as well be boxes with “???” written in them.<p>The maintainers of the me_cleaner script likely have the clearest view of what is known.<p><a href="https://github.com/corna/me_cleaner">https://github.com/corna/me_cleaner</a>
> It's responsible for initialising the chip and getting it out of bed enough to the point where at least one of the main cores can run using cache-as-RAM mode<p>The somewhat surprising but true implication is that on boot, the CPU is initialized before the RAM is initialized. So there is a window of time during boot when the main core on the CPU is running instructions that cannot access the RAM. Even on register-starved x86 it is possible to write code without using RAM, but it certainly seems more convenient to me to treat the cache as RAM.<p>Documentation for a special compiler that compiles to code that doesn't use RAM: <a href="https://github.com/wt/coreboot/blob/master/util/romcc/romcc.1">https://github.com/wt/coreboot/blob/master/util/romcc/romcc....</a>
A modern motherboard can update it's BIOS from a USB stick WITHOUT a CPU or memory installed.<p>Think about that. The motherboard "knows" how to read a FAT file system from a USB mass storage device, verify it's digital signature and flash it with no main CPU or memory.
This reminds me of the "It's Time for Operating Systems to Rediscover Hardware" talk by Timothy Roscoe:<p><a href="https://www.usenix.org/conference/osdi21/presentation/fri-keynote" rel="nofollow">https://www.usenix.org/conference/osdi21/presentation/fri-ke...</a>
As the author of <a href="https://superuser.com/a/347115/38062" rel="nofollow">https://superuser.com/a/347115/38062</a> and <a href="https://superuser.com/a/345333/38062" rel="nofollow">https://superuser.com/a/345333/38062</a>, you have my sympathy about the "pack of lies" involving real mode and several wrong combinations of selector and offset.
Much of the openness of Power7/8/9 was <i>encouraged</i> by Google who wanted to have control over all the firmware, even the secret firmware. I think Google is also auditing PSP/ME source code but the public only sees the audit results.
I miss these kinds of articles on the net. Is anyone else reminded of the CPU Praxis articles that were part of ARS Technica's early rise to popularity? I really miss those. This article, is of course, much shorter, but still, I miss that sort of content on the internet.
A while ago I bought some older AMD 8350 systems, which apparently are the last without a PSP, the platform security processor.<p>I did this as a sort of 'just in case' setup, was planning to put OpenSolaris on it and run things under Zones or LX zones and to run it as a backup server. Fast enough to get some work done and possibly more secure if the PSP is ever used/broken maliciously...
> The Self-Boot Engine (SBE) (quantity: 1) is a core which is responsible for booting the entire system. It's responsible for initialising the chip and getting it out of bed enough to the point where at least one of the main cores can run using cache-as-RAM mode; it does little after that point. It has some SRAM to do its work in and uses a slightly custom variant of the 32-bit Power ISA, extended to support 64-bit loads and stores using adjacent GPR pairs. This core design is known as a PPE. It's the first thing that runs on the CPU die.<p>What I’m curious about is how does the ‘Self Boot Engine’ initialize itself in the first few miliseconds?<p>Maybe, a motherboard chip does the actual work, but that just invites the same question, at some point something must be initializing itself, how?
I was surprised when I read how the Raspberry PI's GPU handles the booting.<p><a href="https://forums.raspberrypi.com/viewtopic.php?t=266130" rel="nofollow">https://forums.raspberrypi.com/viewtopic.php?t=266130</a>