Conway's FPGA game of logical life with Neural Nets

Consider Conway&#x27;s Game of Life. Each cell can be born, live, or die. That is a 1-bit gate. The gates change based on a universal &quot;clock&quot;, i.e. once per cycle.<p>It has already been shown that Conway&#x27;s game of life is Turing complete. People have created a whole CPU in the game.<p>Now assume that each cell can be implemented as a 2-bit lookup table. Clearly one can create a game of life simulation where each 2-bit table either computes a 0 or a 1. That would be an exact simulation of Conway&#x27;s game.<p>A generalization of the game would be that each cell can accept 2 input bits and would compute a bit output bit using a lookup table. Thus a cell could output compute any possible combination of 2 bits. A cell could compute an XOR, AND, OR, NOT, 0, 1, etc. Indeed, by ganging together multiple cells any combinatorial logic function could be implemented.<p>A second generalization is to create &quot;clock domains&quot; so each cell only computes when a &quot;clock&quot; signal arrives. Assume that the clock signal is not universal but that many clocks exist that control a subset of the cells (clock domains).<p>The cells have &quot;memory&quot; as they continue to assert their output bit at every clock tick.<p>Cells can be born, live, die, or change their lookup table value based on the rules.<p>Now you have a &quot;Cellular FPGA&quot;. But this FPGA can grow and adapt dynamically rather than being pre-programmed.<p>What are the new Conway&#x27;s rules for such a simulation?<p>Now consider what happens when we try to architecture a Neural Network on this cellular FPGA. Each &quot;neuron&quot; is a combinatorial logic &quot;cell&quot; that computes a weighted function of its inputs and bias. The Neural Net can adapt because weighted logic &quot;cells&quot; that fall to 0 weights can simply &quot;die&quot; and be reborn as something else in a circuit being &quot;born&quot; later.<p>Now consider creating real, physical wafer-scale hardware that computes this way using a whole-wafer &quot;Conway chip&quot;. The whole physical chip &quot;learns&quot;. https:&#x2F;&#x2F;www.cerebras.net&#x2F;blog&#x2F;wafer-scale-processors-the-time-has-come&#x2F;