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RISC-V Instructions

31 pointsby robalnialmost 2 years ago

2 comments

sylwarealmost 2 years ago
What seems to be missing are the hardware optimized and accelerated short and big memcpy&#x2F;memset.<p>On x86_64, on modern micro-archs, &quot;rep stos[bwdq]&quot; and &quot;rep movs[bwdq]&quot;. I bet that, in modern binaries, memcpy&#x2F;memset call sites are actually place holders for such instructions (before the memory segment goes back to Read&#x2F;Executable), registers are rdi,rsi,rdx (rcx would be pushed on the stack or the code generated to account for just rcx availability on the call site).<p>Also, expect x86_64 -&gt; risc-v port bugs because to: byte-&gt;byte word-&gt;halfword doubleword-&gt;word quadword-&gt;doubleword
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gary_0almost 2 years ago
Does anyone have something like this for amd64 or aarch64?<p>Might be useful when I&#x27;m tinkering with my toy compiler.
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