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Intel Meteor Lake Architecture

108 pointsby SandraBuckyover 1 year ago

12 comments

thunderbird120over 1 year ago
Will be interested to see how this first(ish) gen of Intel's disaggregated chips pan out. I've been needing to replace my laptop and these seem like they have the potential to be extremely nice for a mid range machine with long battery life. The new scheduler hierarchy is especially interesting given how much of the physical chip they can avoid powering on at all for most simple tasks. For a lot of light use cases the entire "real" CPU and GPU parts of the silicon can be completely dark since the SOC has two tiny cores to run things and other necessary parts things like the video decode silicon were separated from the GPU.
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transputeover 1 year ago
<i>&gt; The “South” IO fabric is ordered, but non-coherent and PCIe-based. It is home to Wi-Fi and Bluetooth, PCI Express connections, Sensing, USB 3&#x2F;2, Ethernet, the Power Management Controller (PMC), and Security controllers.</i><p>Does &quot;Sensing&quot; refer to human presence based on camera and radio (Wi-Fi, UWB) imaging?<p><a href="https:&#x2F;&#x2F;lkml.org&#x2F;lkml&#x2F;2023&#x2F;2&#x2F;12&#x2F;314" rel="nofollow noreferrer">https:&#x2F;&#x2F;lkml.org&#x2F;lkml&#x2F;2023&#x2F;2&#x2F;12&#x2F;314</a><p><pre><code> Intel Visual Sensing Controller (IVSC), codenamed &quot;Clover Falls&quot;, is a companion chip designed to provide secure and low power vision capability to IA platforms. The primary use case of IVSC is to bring in context awareness. IVSC interfaces directly with the platform main camera sensor via a CSI-2 link and processes the image data with the embedded AI engine. The detected events are sent over I2C to ISH (Intel Sensor Hub) for additional data fusion from multiple sensors. </code></pre> <a href="https:&#x2F;&#x2F;www.techpowerup.com&#x2F;276114&#x2F;new-intel-visual-sensing-controller-chip-to-give-next-gen-pcs-ability-to-adapt-to-surroundings" rel="nofollow noreferrer">https:&#x2F;&#x2F;www.techpowerup.com&#x2F;276114&#x2F;new-intel-visual-sensing-...</a><p><pre><code> The company didn&#x27;t detail how it goes about this, but technologies already exist to combine visual input from the PC&#x27;s cameras; radio from the PC&#x27;s antennas, audio from its mic array; to form a picture of its surroundings. </code></pre> <a href="https:&#x2F;&#x2F;community.intel.com&#x2F;t5&#x2F;Blogs&#x2F;Tech-Innovation&#x2F;Client&#x2F;Wi-Fi-Sensing-Adding-Sensing-Capability-To-Intel-Wireless&#x2F;post&#x2F;1416624" rel="nofollow noreferrer">https:&#x2F;&#x2F;community.intel.com&#x2F;t5&#x2F;Blogs&#x2F;Tech-Innovation&#x2F;Client&#x2F;...</a><p><pre><code> With an initial focus on respiration detection, we hope to extend the technology to detect other physical activities as well. Intel Labs will demonstrate an early prototype of breathing detection ... The solution detects the rhythmic change in CSI due to chest movement during breathing ... The respiration rates gathered by this technology could play an important role in stress detection and other wellness applications.</code></pre>
kristianpover 1 year ago
Interesting to see how efficient these are for office&#x2F;coding (e.g. typing into vscode) tasks. Will the cpu tile be off most of the time or will it take some years before applications and OS are tuned to avoid cpu tile wakeups.<p>Also how good will the p-cores be compared to previous gen?<p>Are the avx-10 instructions going into this generation?
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kwanbixover 1 year ago
I still wonder how Apple was able to achieve such an incredible performance per watt ratio compared to Intel and AMD. Anybody knows how they let Apple do it?
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keepamovinover 1 year ago
It&#x27;s a good name. Why didn&#x27;t they call it Crater Lake tho?<p><a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Crater_Lake" rel="nofollow noreferrer">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Crater_Lake</a>
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Havocover 1 year ago
Mostly interested in the npu. Most npus are pretty useless for cutting edge ai
sva_over 1 year ago
Any word on how many TFLOPs that NPU could achieve on the high-end chips?
KingOfCodersover 1 year ago
Intel is taking two pages from the Apple ARM book: smaller cores but bigger caches (for more performance and less power) and main memory on the chip (for more performance and less power).
MangoCoffeeover 1 year ago
&gt;Meet Meteor Lake’s Tiles<p>isn&#x27;t &quot;Tile&quot; is basically chiplet? why not just call it chiplet?
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eBombzorover 1 year ago
So a more advanced and feature rich version of Ryzen&#x27;s IO die, with dedicated silicon for AI of course.<p>Can&#x27;t wait for Microsoft and Intel to team together to make an ultra AI search bar that can finally find files properly like back in Windows 7...
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sillywalkover 1 year ago
I wish Intel would switch to a new code-name scheme. There&#x27;s been enough &quot;Lakes&quot;.
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dschuetzover 1 year ago
The article (or Intel) do not disclose up to how many cores that new architecture is designed for, and I am certain Intel would say something like &quot;With our P-, E-, LE-cores designed architecture(tm) the core count does matter anymore&quot;.<p>Also the SOC with built-in AI engine. Oh boy, I wonder how long it will take for AI-assisted malware, or botnets to emerge. Exciting times!
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