Apple today introduced M3 range of laptops which uses 3-nm technology [1]<p>Moore's law has been driven primarily by the reduction in transistor sizes. How far does this go?<p>Can we go to sub-1nm or is there a limit here and then Moore's law ends? AFAIK at smaller sizes quantum tunneling starts coming into picture. What happens when we hit that limit?<p>[1]https://www.apple.com/macbook-pro/
A frustrating thing is that the process node name has decoupled from the feature size:<p>> Later each new generation process became known as a technology node or process node, designated by the process' minimum feature size in nanometers (or historically micrometers) of the process's transistor gate length, such as the "90 nm process". However, this has not been the case since 1994, and the number of nanometers used to name process nodes (see the International Technology Roadmap for Semiconductors) has become more of a marketing term that has no standardized relation with functional feature sizes or with transistor density (number of transistors per square millimeter).<p>So each recent process has an explanation on Wikipedia like<p>> The term "3 nanometer" has no relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.<p>Respectively from<p><a href="https://en.wikipedia.org/wiki/Semiconductor_device_fabrication#Process_size" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/Semiconductor_device_fabricati...</a><p><a href="https://en.wikipedia.org/wiki/3_nm_process" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/3_nm_process</a>
Short answer: it isn't, this 3-nm is a marketing term, they keep redefining the term to use a lower and lower number.<p>Transistor body dimensions is at or below about 7nm start having some quantum effects.<p>Here's a reddit post where there's more detail about the physics and science behind this: <a href="https://www.reddit.com/r/askscience/comments/itiuw8/how_are_chip_manufacturers_getting_around_quantum/" rel="nofollow noreferrer">https://www.reddit.com/r/askscience/comments/itiuw8/how_are_...</a>
There's a lot more to optimizing comouting than just the size and number of transistors. Such as branch prediction and many other aspects.<p>Also, gaming and ML training rely on massive parallelism. So that's another paradigm.<p>More new paradigms like memory-centric and/or analog computing for AI will be commercialized in the next several years.