What's the avg spacing on atoms in a silicon matrix anyway? Something on the order of 0.2nm (2A)? So are we now nearing a point where 1 extra atom is 10% error in a single dimension?<p>Would be grateful if someone who actually understands this stuff would care to illuminate my speculation further?
I hope Intel and Samsung will have much success, because TSMC betrayed customers by exclusively providing all top-level manufacturing capacity only to Apple and handling anyone else as a second class citizen.