I would love to see a clear roadmap from the EU (not been successful searching)<p>My take on this is<p>1. this is less about competitiveness at the cutting edge and more about security and economic on-shoring<p>2. building chips on-shore at the 40-20nm level massively reduces risk, increases the likelihood smaller states can build locally and solves for most chip needs<p>3. chips we need are rarely the cutting edge AI stuff. The vast volume of chios will go in as controllers on screens, USB connectors and so on. Building plug and play alternatives will give local manufacturers choices, and incentives will help.<p>4. the big win is security. Does the CEO of sensitive company, the head of security services and the general in charge of procurement use keyboards, cpus motherboards and monitors made from open source chips manufactured in a trusted nation? What is the BOM for the challenger tank - how many chips in there that are made by whom and ...<p>the process is long and arduous and the risks are huge.<p>But we make tanks from steel other materials made in "favoured nations" - surely the same applies to silicon?
It's a cool project but I do wish these open source processor initiatives targetted more realistic design points.<p>In particular there's often a desire to push out of order design into the micro-architecture where the resulting performance just doesn't justify it. In this they're achieving a CoreMark/MHz of 2.44 (from the paper here: <a href="https://upcommons.upc.edu/bitstream/handle/2117/384912/sargantana_preprint.pdf" rel="nofollow noreferrer">https://upcommons.upc.edu/bitstream/handle/2117/384912/sarga...</a>). This is very low performance (on a par with the Arm M0+). Now CoreMark certainly isn't the be all and end all of Benchmarks. In particular it has very little relevance to high performance compute or application cores in general. However it's a useful performance smoke test. It is easy to perform well e.g getting close to 1.0 IPC for a single issue design such as Sargantana, CoreMark doesn't really stress the memory system so a major source of stalls that you need to hide latency for just isn't there. So if you're not hitting that you've definitely got work to do on the microarchitecture. They may well have been better off trying to build something simpler and putting more design time into improving the performance of the basic microarchitecture.<p>The other crucial aspect that's often overlooked is verification. This is a major part of producing a new production quality CPU design and it doesn't appear to be discussed in the paper at all. Maybe once they've released the RTL they'll also release the testbench so you can see what they have done.
For those of you who don't speak Catalan, "sargantana" is a common little local lizard (Podarcis hispanicus, "Iberian wall lizard"). Of course the chip family (Lagarto) just means "lizard" in Castilian.
Here's a pre-print paper I found:<p>Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI<p><a href="https://upcommons.upc.edu/bitstream/handle/2117/384912/sargantana_preprint.pdf" rel="nofollow noreferrer">https://upcommons.upc.edu/bitstream/handle/2117/384912/sarga...</a><p>RV64GC with a subset of the v0.7.1 vector extension. 1.26GHz nominal clock on a 22nm process.
> The BSC, Europe's leading developer of open source computing technologies<p>> The fact that the [..] architecture [..] of these new processors is open source, and therefore non-proprietary and accessible to all, reduces technological dependence on large multinational corporations<p>I hadn't heard of either BSC nor Open Source Computing before. I'm curious though, are there a lot of people out there who are not tied to large corporations and who have the knowledge and the means to produce computer hardware? Are there hobbyists out there producing their own custom chips and graphics cards?
> The Barcelona Supercomputing Center [...] presented on Wednesday the new Sargantana chip, the third generation of open source processors designed entirely at the BSC.<p>> Researchers from other universities and research centres such as the Centro de Investigación en Computación del Instituto Politécnico Nacional de México (CIC-IPN) [...] have participated in the development of Sargantana.<p>So this was designed entirely in Spain but it is also joint work with a university in Mexico ;-) Nice project though; I've visited BSC and they do a lot of cool work there.
Unrelated note: BSC is a location in the unapologetically crazy HBO series "30 coins" season 2, some cool sequences there involving a group visit.
Shout out to affordable subsidized <a href="https://en.wikipedia.org/wiki/Multi-project_wafer_service" rel="nofollow noreferrer">https://en.wikipedia.org/wiki/Multi-project_wafer_service</a><p>Be it googles OpenMPW Free Silicon Chip Program <a href="https://developers.google.com/silicon" rel="nofollow noreferrer">https://developers.google.com/silicon</a> (still active?)<p>Or the EU subsidized multi project wafer <a href="https://europractice-ic.com/schedules-prices-2023/" rel="nofollow noreferrer">https://europractice-ic.com/schedules-prices-2023/</a>
What about this chip is open source? As far as I can tell, nothing. It frustrates me to no end that closed, secret efforts inherit the “open source” branding just because the specification they implement is participatory and royalty free.
Does anyone know a decent RISC-V developer kit that one can buy in the Bay Area today? Or rent somewhere in the cloud? I want to start porting our C libraries to RISC-V.
Very cool, I just got a MangoPi and I'm excited to get some stuff running on it.<p>I imagine RISC-V is the future. None wants to pay licensing fees to Arm
Interesting. It'd be nice to know if they're going to focus on HPC loads or hobby/consumer too. I should check to see if I still know people around the BSC :P