What's interesting is that these devices don't need 321+ litho steps; the vertical layers are all defined with deposition. Lithography step count isn't layer dependent it seems.<p><a href="https://youtu.be/ANHzVOiUwGI" rel="nofollow">https://youtu.be/ANHzVOiUwGI</a><p><a href="https://thememoryguy.com/3d-nands-impact-on-the-equipment-market/" rel="nofollow">https://thememoryguy.com/3d-nands-impact-on-the-equipment-ma...</a>
When I was in school studying NAND devices (2004-2010) we were quite apprehensive at the long term quantum stability of 4-layer devices.<p>This (the past 20 years of improvement) is an incredible feat of engineering.
What does 'layer' mean in this context? I'm only familiar with planar style logic process nodes which have maybe up to 20 layers (and way more lithography steps to manufacture those layers), but I am completely ignorant of how the term is used for a flash process node.<p>How many layers are needed for each physical cell?
Is it 1,2, or a lot more? Is this effectively 321 physical TLC cells stacked vertically and some planar style logic at the bottom of the stack.<p>Also, where do multiple pieces of silicon factor into this - I assume we might be up to 16 silicon dies deep with through-silicon-vias, which would mean a cross section of a package could actually have 5000 layers - that sounds crazy!
If I am reading this correctly, this is still the same 1Tb per die but with 321 layers, meaning up to 2TB / package. The package should now be under 100mm2.<p>This would hopefully bring down the price of 4TB and 8TB SSD in the near future.
insider info: all the top talent at Samsung left for SK Hynix after government stepped and forced DEI on Samsung leading to unqualified managers ruining Samsung's culture of innovation and rewarding experimentation.