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Disabling Zen 5's Op Cache and Exploring Its Clustered Decoder

116 pointsby mfiguiere4 months ago

4 comments

sitkack4 months ago
If you enjoy the science of injecting slowness to determine which component has the largest impact on performance, you would enjoy this work by Emery Berger.<p>Coz: Finding Code that Counts with Causal Profiling <a href="https:&#x2F;&#x2F;arxiv.org&#x2F;abs&#x2F;1608.03676" rel="nofollow">https:&#x2F;&#x2F;arxiv.org&#x2F;abs&#x2F;1608.03676</a><p>&quot;Performance (Really) Matters&quot; with Emery Berger <a href="https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=7g1Acy5eGbE" rel="nofollow">https:&#x2F;&#x2F;www.youtube.com&#x2F;watch?v=7g1Acy5eGbE</a>
sylware4 months ago
With all the hardware &quot;security&quot; issues discovered in the last few years, CPU designers should provide the possibility to turn off many of hardware features to end up with a brutal in-order basic CPU.<p>Performance will be destroyed for somewhat more confidence in their &quot;security&quot;.
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ksec4 months ago
&gt;if we step back a few months to Hot Chips 2024, AMD, Intel, and Qualcomm all gave presentations on high performance cores there. All three were eight-wide, meaning their pipelines could handle up to eight micro-ops per cycle in a sustained fashion.<p>&gt;Zen 5 is the only core out of the three that couldn’t give eight decode slots to a single thread.<p>If you add Apple and ARM. That is the only core out of the five. I am thinking if Zen 6 will be something different. Right now Intel is iterating like crazy. And Zen 6 is still quite far off.
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metadat4 months ago
How is ChipsAndCheese work funded? Their analysis is consistently informative and well-done.
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