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Opensouce RISC-V CPU core implemented in Verilog from scratch in one night

4 pointsby delduca2 months ago

2 comments

brucehoult2 months ago
See the original 2018 post<p><a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=17852876">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=17852876</a>
Rochus2 months ago
&gt; <i>implemented in Verilog from scratch in one night</i><p>Cool, but the &quot;night&quot; actually started in 2018 and lasted over seven years and 384 commits so far ;-)
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