We're a small team of FPGA and software developers applying statistics and machine learning to solve FPGA timing closure and place-n-route problems. After experimenting with synthesis and place-n-route tools, we found that a lot more mileage can be gotten out of current tools.<p>We'd like to ask the community for help to test these ideas.<p>Unlike random seed sweeps, our compilation builds are focused and use probability to guide FPGA designs towards desired results. The algorithm learns from past builds and improves itself based on device, design and tool characteristics. Lessons learned are then saved for reference.<p>To try this out, we've built a software plugin for major FPGA tools, and are making an API so that <i>every FPGA designer</i> can tap a shared database of "best practices" and apply his/her own algorithm to solve problems.<p>If you have a hard, annoying timing/area/power problem, please share the design with us so that we can improve. (NDAs most welcome)<p>In return, we'll do our best to improve your design's performance and solve its problems. If you like, we'll gladly give you a license once the tool is ready and be your friend for life!<p>To share a design, simply:<p>1) zip your project files;<p>2) add them into the upload box at http://www.plunify.com/callfordesign/cfd.php<p>3) tell us what tool version it needs;<p>4) (if you like) tell us who you are so we can share the results and tool when they're ready.<p>or just send me a URL (email address in my profile)<p>After testing designs from github, opencores, etc. we learned some requirements that make a design more "real".<p>They are:<p>- above 50% utilization;<p>- has a real application (logic wasn't randomly generated to fill the FPGA);<p>- can compile successfully<p>Please comment, question and most of all, consider sharing a design so we can make a difference!