Hm... the link only talks about the CPU, but calls itself a SoC. There's a lot more than needs to go on any chip that calls itself a "SoC", and much of it is very poorly served by existing "open source" solutions:<p><pre><code> + DRAM
+ I2C
+ GPIO (with stuff like 3.3v, tristate outputs, pull up/down, etc...)
+ USB2 host/device
+ SD/MMC
</code></pre>
And that's just at the very basic level. Once you get into the consumer world you need to start talking about video output, camera input, video decode and encode acceleration, programmable GPUs,...<p>Really the CPU is, in some sense, the most solved problem from the perspective of open source. The designs themselves may be closed IP, but the instruction sets are meticulously documented and their behavior is very standard across many vendors and ISAs.
RISC-V looks like MIPS but with some of the more dubious design decisions of the time (e.g. branch delay slots) fixed. The mix of 16-bit and 32-bit instruction lengths is reminiscent of ARC.<p>In other words, the characteristics of SoCs using this core will likely be <i>very</i> similar to the many out there using MIPS: cheap and simple, with performance that's acceptable for applications like routers and other embedded devices.
That hardware implementation of RISC-V listed on their website is written in Scala (using Chisel). That's very cool. I want to see synthesis results.
<i>Volume silicon manufacture is planned</i><p>I highly doubt it. But if it's true, that would be the missing link for all open source hardware design.<p>It would also be nice if they gave some idea of the kind of performance or implementation they are considering.
I'm not familiar with the IP issues. Would it be possible to center open-source processor development around the ARM instruction set?<p>It looks like the privileged part of the RISC-V ISA is not finished yet. This is a great project, but it seems a long way off.
(Disclaimer: I'm developing my own RV64 FPGA implementation.)<p>I wish the page was a little more clear on what the intentions are, etc, but seeing RV64 in silicon would be immensely exciting. Producing a simple in-order machine, even with usual set of peripherals isn't very hard at all and nor that expensive on an older process node, but there's a world of difference if we start talking superscalar out-of-order multi-core SMP. Seeing OpenRISC on the Advisory Board I suspect it's more the former than the latter.