I'd really like to see the full ISA, etc for the chip. A few years ago, I was doing research on building a byte code based vm after working through Peter Michaux "Scheme From Scratch" <a href="http://peter.michaux.ca/articles/scheme-from-scratch-introduction" rel="nofollow">http://peter.michaux.ca/articles/scheme-from-scratch-introdu...</a>. (I highly recommend running through his code, but do the GC earlier, it's easier to get it from the start than to try to add it.) I couldn't find anything online listing the kinds of instructions you'd want in a lisp chip.
Yes, it can be done, but the half-dozen or so LISP machines of the 1980s were not very successful. Price/performance was worse than compiled LISP on common CPUs.<p>There's no indication of hardware support for garbage collection. It would probably be more useful to have tag bits to support GC than a LISP-oriented instruction set, especially if it allowed concurrent GC.
Talking about Lisp machines. I don't know much about these things but I was thinking about them recently when Hewlett Packard announced its so-called <i>Machine</i>^1. They want to build a new kind of OS for it, but wouldn't a Lisp machine just do?<p>[1] <a href="http://www8.hp.com/hpnext/posts/discover-day-two-future-now-machine-hp" rel="nofollow">http://www8.hp.com/hpnext/posts/discover-day-two-future-now-...</a>
I've heard a few people suggest that with single core performance stagnating we may see more ASICs. I admit I'm skeptical, but this line of development does seem worth exploring.