Stan Williams of HP Labs gave a talk recently at Rice, his alma mater. He was describing the "HP Machine" they are working on, with memristors at the bottom of a hardware and software stack rearchitected from scratch. Don't look to be able to buy any memristors from HP anytime soon. HP predicts that their own internal demand, in producing the HP Machine, will consume all their memristor production for years.
Oh that is pretty clever. I wonder what the write time is. Even a reliable 6 level memory would be useful giving you four useful states (2 bits), a non-initialized, and an initialized undef state.
<p><pre><code> For example, the largest unsigned binary 64-bit integer—18,446,744,073,709,551,615—
could be held in 20 bits instead of 64.
</code></pre>
This should read "could be held in 20 digits instead of 64 bits."
This is an interesting implementation of the memristor, but I still think the real breakthrough will be in the two state memristor [1]. Once memristor fabrication technology is mature, we are going to see a massive paradigm shift away from the Von Neumann architecture.<p>All the details are in the linked video by HP's Stan Williams. Definitely worth a watch if you're interested in the future of computing<p>1. <a href="https://www.youtube.com/watch?v=bKGhvKyjgLY" rel="nofollow">https://www.youtube.com/watch?v=bKGhvKyjgLY</a> (start at 38m for future computing implications)<p>EDIT:<p>Another video [2], but a bit more in depth. Recommended if the material in the first was a bit confusing as Stan was short on time to explain some of the details.<p>2. <a href="https://www.youtube.com/watch?v=QFdDPzcZwbs" rel="nofollow">https://www.youtube.com/watch?v=QFdDPzcZwbs</a>
Here is the paper for any one curious in a look at the actual configuration of the nanowire device: thankfully there is no pay-gating <a href="http://pubs.acs.org/doi/abs/10.1021/nn505139m" rel="nofollow">http://pubs.acs.org/doi/abs/10.1021/nn505139m</a>
I found interesting that world's first mechanical computer, Charles Babbage's "Analytical Machine" had a base-10 fixed point arithmetic [1], and we could soon have base-10 RRAM...<p>[1] <a href="https://en.wikipedia.org/wiki/Analytical_Engine" rel="nofollow">https://en.wikipedia.org/wiki/Analytical_Engine</a>
so how is that any different from NAND MLC and TLC?
I bet they already got it patented with a cute "on a memristor" at the end of application title.