Here's a (somewhat overly cynical) marketing->reality translation I performed on their whitepapers for one of my bosses. Obviously, given that I only looked at the whitepaper, some of my interpretation might be slightly inaccurate, but I think it's close enough.<p>(He was interested in running x264 on it.)<p><i>The TilePRO64 Processor is programmed in ANSI standard C</i><p>You'll need to use our custom proprietary (and bad) compiler, and we probably won't give you an assembler.<p><i>32-bit VLIW processors</i><p>You'll have to spend thousands of man-hours rewriting all of your assembly code.<p><i>H.264 HD encode for 10 streams of 1080p (baseline profile)</i><p>Even when we make every last possible marketing cheat that we can possibly make with custom CPU-specific code, we can only get 10 streams going realtime, barely more than what one can do on a standard dual-Nehalem system with x264 (with similarly marketing-cheat level settings).<p><i>700mhz, 866mhz operating frequency</i><p>Unless every part of your application is embarassingly parallel (read: not x264), there's no way you'll get it to run at any reasonable speed on this thing.<p><i>iLib APIs for efficient inter-tile communication</i><p>You'll have to rewrite your code yet again to use a new library.<p><i>5.6 Mbytes of on-chip cache</i><p>Our CPU has an embarassingly small amount of cache per-core, which is why we can get so many onto the die at such lower power usage. Your program will be overwhelmed by cache misses.<p><i>19-23W @ 700mhz for typical applications</i><p>We're selling a big fancy DSP, not a real general-purpose processor. If you want to get good performance out of it, you'll probably have to rewrite a lot of code.
There is much more technical information on charlie's page
<a href="http://www.semiaccurate.com/2009/10/29/look-100-core-tilera-gx" rel="nofollow">http://www.semiaccurate.com/2009/10/29/look-100-core-tilera-...</a><p>Although generally the posts there are just rants this one is quite good
This article is not informative (or technical) enough, IMHO. It lacks :<p>- The instruction set used is a MIPS-derived VLIW instruction set according to <a href="http://en.wikipedia.org/wiki/TILE64" rel="nofollow">http://en.wikipedia.org/wiki/TILE64</a><p>- It needs to say that 99% of developers don't really care about instruction set as they use higher-level languages.<p>EDIT: A new cpu architecture is always an exciting sight, though.
Interesting architecture but the amount of information available publically is limited? For example, I was trying to find out if it will be suitable for parallel floating point workloads but I don't see any mention of floating point performance on the company webpage. Would also be nice to see some benchmark numbers done by a 3rd party. Never believe what the vendors say about their own products.
This chip looks cool, but "FP code is still frowned upon" is a shame. I would actually be more interested in a 100 core chip, if its cores were tuned to accelerate OpenCL.