Create Your Own CPU on an FPGA

Some guy started a series some weeks ago on designing a CPU for an FPGA: <a href="http:&#x2F;&#x2F;labs.domipheus.com&#x2F;blog&#x2F;designing-a-cpu-in-vhdl-part-1-rationale-tools-method&#x2F;" rel="nofollow">http:&#x2F;&#x2F;labs.domipheus.com&#x2F;blog&#x2F;designing-a-cpu-in-vhdl-part-...</a><p>For those interested in a more complex processor, RISC-V seems to be a processor on par with ARM in terms of features: <a href="http:&#x2F;&#x2F;riscv.org&#x2F;" rel="nofollow">http:&#x2F;&#x2F;riscv.org&#x2F;</a>

Does anyone have knowledge about the comparison of different FPGA boards?<p>I&#x27;ve seen the Mojo v3 from Embedded Micro, the Papilio line of dev boards, and the miniSpartan6+ from Scarab Hardware.<p>It looks like all these dev boards are pretty similar since they use almost identical xilinx chips. Ideally, I&#x27;d like to find a board for which there is a robust community, good support, lots of examples, and has enough capacity&#x2F;performance to take on more complicated projects with increased learning&#x2F;skill.<p>I&#x27;m leaning towards the Mojo v3 board, since it seems very easy and has shields to expand capability, but does anyone have any experience, recommendations, or &quot;I wish I had known...&quot; stories for FPGA development?

... using the &quot;Lucid&quot; HDL, which at first glance seems like a de-crufted Verilog.

I&#x27;ll just leave this here: <a href="https:&#x2F;&#x2F;github.com&#x2F;zeusk&#x2F;CS242" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;zeusk&#x2F;CS242</a><p>I did this during my sophomore year, didn&#x27;t care much about implementing a proper memory implementation as that was way beyond the scope of our course.

Every Computer Engineering undergrad is rejoicing somebody just did their project for them.

Does anyone have any tips on determining if a given CPU core will fit onto a given FPGA? Most of the boards in the hobbyist price range seem kinda ... underwhelming.

No discussion of CPU design is complete without trying to run your design as fast as possible. That&#x27;s how people discovered that pipelining is good, and a flat implementation (such as the one in that code) is slow.