Maybe Clockless Chip Design's Time Has Come

This field has a well established name: asynchronous logic&#x2F;circuit.<p>The author of the article failed to even mention once this term, instead repeating the term “clockless” as he was in some kind of branding spree.<p>Furthermore one of the article&#x27;s tags was “apple”, despite AFAIK the content not being affiliated with apple in any way.

Another very interesting async design is GreenArrays GA144: &quot;This very powerful and versatile chip consists of an 18x8 array of architecturally identical, independent, complete F18A computers, or nodes, each of which operates asynchronously. Each computer is capable of performing a basic ALU instruction in ~1.5 nanoseconds for an energy cost on the order of 7 picojoules&quot;. Programmed in Forth. <a href="http:&#x2F;&#x2F;www.greenarraychips.com&#x2F;index.html" rel="nofollow">http:&#x2F;&#x2F;www.greenarraychips.com&#x2F;index.html</a>

Not that the article is particularly detailed, but squinting at the clock diagram for Wave Semi, it appears to be a some kind of token passing, where the token is the clock.<p>I guess this question is for the semi- folks out there: given any n-bit boolean function, for smallish n, is there a way to implement the function so that the output is rock-stable (within reason) and only flips if given an input flip the corresponding function flips?<p>Because, if not, I don&#x27;t see how this clock passing system won&#x27;t require factoring in logic delay.<p>I&#x27;m sure a lot of details have been elided. Also, if it isn&#x27;t apparent, I have no logic design knowledge.<p>All I know, from an outsider&#x27;s perspective, having a global clock is ludicrous. When will designers finally kill it?! Us software people have had to kill the concept of intrinsic clocks with our consensus protocols for a while now...

Asynchronous circuits: <a href="https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Asynchronous_circuit" rel="nofollow">https:&#x2F;&#x2F;en.wikipedia.org&#x2F;wiki&#x2F;Asynchronous_circuit</a>

I think there is a technological path for gradually introducing synchronous design in clocked world: you can give them clocked inputs without problem, and you can gate their output at their worst propagation time without problem either.<p>I think with such an easy technological path, there is no intrinsic reason not to have them around us, even exposed as clocked systems. If someone told me today that there already are synchronous blocks in a famous silicon chip I would certainly not be surprised.<p>For example, I&#x27;m not a silicon guy so I&#x27;m guessing, but adders are generally exposed as one cycle instructions in software, but they still have to propagate the carry on the width of the word, so I guess adders are simply a tree of gate that synchronously propagate and we know the carry propagates faster than the clock tick.

I recently asked an Intel chip designer if asynchronous circuits could be a way to deal with stalling of Moore&#x27;s Law and he was adamant that asynchronous circuits are a &quot;fantasy.&quot; His argument was that even though synchronous use about 20% of the energy on a modern, chips, with asynchronous you still need to pass around synchronization tokens which would double the energy required and worse it would be on the critical path.

Fulcrum Microsystems was a Clockless ASIC startup that was acquired by Intel in 2011 for their Ethernet switch silicon technology. <a href="http:&#x2F;&#x2F;newsroom.intel.com&#x2F;community&#x2F;intel_newsroom&#x2F;blog&#x2F;2011&#x2F;07&#x2F;19&#x2F;intel-to-acquire-fulcrum-microsystems" rel="nofollow">http:&#x2F;&#x2F;newsroom.intel.com&#x2F;community&#x2F;intel_newsroom&#x2F;blog&#x2F;2011...</a>

I remember this company from about 10 years ago. I don&#x27;t remember the company name, but the logic was called Null Control Logic then.

See also, FLEET[1]. I&#x27;m surprised this hasn&#x27;t gained more traction(or at least hype). I saw Sutherland give a talk about it in 2011&#x2F;2012 or so.<p>[1]<a href="https:&#x2F;&#x2F;inst.eecs.berkeley.edu&#x2F;~cs152&#x2F;fa06&#x2F;lecnotes&#x2F;async.pdf" rel="nofollow">https:&#x2F;&#x2F;inst.eecs.berkeley.edu&#x2F;~cs152&#x2F;fa06&#x2F;lecnotes&#x2F;async.pd...</a>

I recently dropped a lot of links to asynchronous cell libraries, chips, and so on in this comment:<p><a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=10621937" rel="nofollow">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=10621937</a><p>Just in case pro&#x27;s want to comment on any of it or think it&#x27;s cool.

&gt;They also had to invent a new type of gate – one that switches based on the sum of the number of its input that are at logic 1.<p>What? Isn&#x27;t that just AND? I wasn&#x27;t really too clever from looking at the diagram provided, so I might be missing something.

Didn&#x27;t some company have a clockless ARM core available a few years back?

I wonder how real time systems would work without a clock to synchronize everything.

Leakage is the big problem in deep submicron. You can&#x27;t keep a state without periodically refreshing it (cf. DRAM). Also, asynchronous circuits are very prone to metastability. If these problems were easily solved, we&#x27;d have seen this old idea be widespread by now.