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Open Source FPGA Toolchain Builds CPU

109 点作者 jamesbowman超过 9 年前

5 条评论

nickpsecurity超过 9 年前
It would be interesting to see someone put JOP on FPGA through the toolchain:<p><a href="http:&#x2F;&#x2F;www.jopdesign.com&#x2F;" rel="nofollow">http:&#x2F;&#x2F;www.jopdesign.com&#x2F;</a><p>Then maybe academics in INFOSEC can try to put JX OS on it for secure, embedded apps:<p><a href="http:&#x2F;&#x2F;www4.cs.fau.de&#x2F;Projects&#x2F;JX&#x2F;" rel="nofollow">http:&#x2F;&#x2F;www4.cs.fau.de&#x2F;Projects&#x2F;JX&#x2F;</a><p>Native Java means no breaking out of JVM&#x27;s model down to weird native code.
sklogic超过 9 年前
Icestorm and yosys are cool!<p>Since then even more CPUs are working on ICE40:<p><a href="https:&#x2F;&#x2F;github.com&#x2F;cliffordwolf&#x2F;picorv32" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;cliffordwolf&#x2F;picorv32</a><p>Or a really small and slow one (smaller than J1, but needs more RAM): <a href="https:&#x2F;&#x2F;github.com&#x2F;combinatorylogic&#x2F;soc&#x2F;tree&#x2F;master&#x2F;backends&#x2F;tiny1" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;combinatorylogic&#x2F;soc&#x2F;tree&#x2F;master&#x2F;backends...</a>
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ZenoArrow超过 9 年前
Will put this here just in case anyone is interested, it&#x27;s a FPGA Hat for the Raspberry Pi, based on the iCE40 FPGA.<p><a href="https:&#x2F;&#x2F;github.com&#x2F;xesscorp&#x2F;CAT-Board&#x2F;blob&#x2F;master&#x2F;README.md" rel="nofollow">https:&#x2F;&#x2F;github.com&#x2F;xesscorp&#x2F;CAT-Board&#x2F;blob&#x2F;master&#x2F;README.md</a>
grandalf超过 9 年前
I was looking at IceStick kits the other day and they appear to be backordered &gt; 11 weeks.
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placeybordeaux超过 9 年前
I always thought the advantage of a FPGA is that they are very fast when programmed for a specific task. This seems like an interesting project, but is there a case where this would be preferred over any given CPU?
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