Updated RISC-V Instruction Set Manual: Version 2.1

From the Preface of the linked PDF:<p><i>This is version 2.1 of the document describing the RISC-V user-level architecture. Note the frozen user-level ISA base and extensions IMAFDQ version 2.0 have not changed from the previous version of this document, but some specification holes have been fixed and the documentation has been improved. Some changes have been made to the software conventions.</i>

Security:<p>It still won&#x27;t do execute-only and true read-only memory. We&#x27;ve had true read-only for ages now on x86, and just got execute-only. You need these: rw- r-- --x<p>It still has poor support for ASLR, especially the limited-MMU variants. Even the most limited version should be able to require that the uppermost address bits be something randomish, even if it&#x27;s only a per-priv-level random cookie.

I guess the privileged ISA still being a draft prevents full application processors from being rolled out. But is there anything preventing micro-controllers being mass produced? Why isn&#x27;t there an Arduino with a RISC-V micro-controller yet?

&quot;We did not include special instruction set support for overflow checks on integer arithmetic operations, as many overflow checks can be cheaply implemented using RISC-V branches.&quot;<p>False. For example, JavaScript add&#x2F;sub will require 3x more instructions on RISC-V than x86 or ARM. Same will be true for any other language requires (either implicitly, like JS, or explicitly, like .NET) overflow checking. Good luck with that, lol.