All AMD ThreadRipper CPU's will have 64 PCIe Lanes

I was of the opinion that Intel will only face real competition when arm reaches parity with desktop class cpu. Nice to see AMD rise back up again. Hope Intel is not able to strong arm the oems like last time when AMD had design wins but Intel using anti competitive practice stalled its growth till it was able to catch-up and later go ahead.

Before you get excited about unleashing the power of 16 cores on your desktop... I have recently upgraded from the 4-core to 6-core i7 with roughly the same frequency&#x2F;turbo and noticed that compile times have actually increased.<p>Disappointing, I thought, especially because in addition to extra two cores I now sport a quad-channel DDR RAM. Well, turns out that compiling my Go projects does not generate enough &quot;hot&quot; threads, and the Linux scheduler keeps moving them around between 6 cores, letting the cores to &quot;cool down&quot; and drop to 1.2Ghz idle frequency. Meanwhile the 4-core box is happily spinning at 3.4-3.8Ghz during the compile cycle.<p>The only way to make the 6-core box to perform was to enable &quot;performance&quot; policy for intel_pstate which leads to the CPU running at its full speed even at idle (not great). Once I did that I saw the performance increase by 50%.<p>Here are the compile times of the same project on both machines with different CPU frequency scaling policies:<p><pre><code> governor&#x2F;cpu 4-core 3.4Gz 6-core 3.3Ghz ------------ ------------- -------------- standard 13 sec 15 sec performance 11 sec 9 sec </code></pre> As far as I know, AMD does not have an equivalent of intel_pstate in Linux kernel and relies on legacy ACPI governor which isn&#x27;t as sophisticated as Intel&#x27;s (where the CPU is more self-regulating) and I wonder what kind of effects to expect in regards to performance &#x2F; power consumption if I go for Ryzen.

The huge number of PCIe lanes is pretty exciting to me. For consumers, the limiting factor in PCs these days tends to be I&#x2F;O. With this, you could have <i>4 PCIe M2 SSDs</i> (that&#x27;s a bit under 16Gbps bandwidth, assuming RAID0), and still have 44 lanes (the number in the top-end Intel CPU) to spare for GPUs and other peripherals.

We all benefit when AMD is a player.<p>And this player is fighting HARD right now. Me gusta.

Salient point:<p>&gt; all 64 lanes being <i>enabled for all ThreadRipper</i> SKUs. This will be broken up into 60+4: <i>60 lanes directly from the CPU for feeding PCIe and M.2 slots</i>, and then another 4 lanes going to the chipset<p>And<p>&gt; the 16 core processor will for most purposes be half of an Epyc processor<p>Epyc (formerly Naples) is the server-grade arch with 8 memory channels, 32 cores and 128 PCIe lanes per socket.

Competition is supposed to bring prices down, yet Intel released i9 processor for an insane prize (nearly 2000$).<p>If AMD manages to ship similar performance (not necessarily higher) at a lower price... Sooner or later Intel will have to slash its prices.<p>Looking forward to such times.

Relevant link [1] for background informations on expected shortcomings of the recently announced concurrent Intel CPUs.<p>[1] <a href="http:&#x2F;&#x2F;semiaccurate.com&#x2F;2017&#x2F;05&#x2F;30&#x2F;intel-announces-x-series-without-details&#x2F;" rel="nofollow">http:&#x2F;&#x2F;semiaccurate.com&#x2F;2017&#x2F;05&#x2F;30&#x2F;intel-announces-x-series-...</a>

Threadripper &amp; EPYC are a truly epic move to jump into the dense GPU workstation and server market! With a Threadripper you get four x16 GPUs without PLX or three + a couple of SSDs.<p>Time for @nvidia to switch the DGX boxes to @AMD CPUs? :)

64 lanes would be good for something like 4-6 GPUs @ 8 lanes per, and some high speed storage&#x2F;networking?<p>Anxiously awaiting Intel&#x27;s &quot;I am not left handed either&quot; response.

Any word from AMD on support for Thunderbolt 3, now Intel are making it available royalty-free?<p><a href="https:&#x2F;&#x2F;newsroom.intel.com&#x2F;editorials&#x2F;envision-world-thunderbolt-3-everywhere&#x2F;" rel="nofollow">https:&#x2F;&#x2F;newsroom.intel.com&#x2F;editorials&#x2F;envision-world-thunder...</a>

Do the extra PCIe lanes help the GPUs for deep learning applications, or is the data typically pretty localized on the GPU board?

Does any remember the DEC Alpha? Windows NT 4.0 was ported to it. The Alpha was a 64-bit RISC processor. (Reduced Instruction Set Computer) An ARM is just an Advanced RISC Machine. RISC architecture has an instruction execution advantage over CISC (Complex Instruction Set Computer) that is what Intel is famous for. Although they did have a i860 and i960 RISC which many of them were for embedded military systems.<p>Other RISC systems were from Silicon Graphics, with their MIPS processor were used for 3D graphic processing. RISC has shown that it has its place in the computing world time and time again.<p>My personal appeal is their low power requirements and compact designs. Obviously cell phone manufactures like it too for the same reasons.

If the clock speeds are decent (and the price is reasonable) this will be my next workstation CPU. Can&#x27;t wait.

I didn&#x27;t see pricing info in the article. Has that been announced anywhere?

I dare say, that might be enough lanes....