Intel Xeon processor with FPGA now shipping

From The Next Platform (<a href="https:&#x2F;&#x2F;www.nextplatform.com&#x2F;2018&#x2F;05&#x2F;24&#x2F;a-peek-inside-that-intel-xeon-fpga-hybrid-chip&#x2F;" rel="nofollow">https:&#x2F;&#x2F;www.nextplatform.com&#x2F;2018&#x2F;05&#x2F;24&#x2F;a-peek-inside-that-i...</a>):<p><i>The initial workload that Intel is targeting is putting Open Virtual Switch, the open source virtual switch, on the FPGA, offloading some switching functions in a network from the CPU where such virtual switch software might reside either inside a server virtualization hypervisor or outside of it but alongside virtual machines and containers. This obviates the need for certain Ethernet switches in the kind of Clos networks used by hyperscalers, cloud builders, telcos, and other service providers and also frees up compute capacity on the CPUs that might otherwise be managing virtual switching. Intel says that by implementing Open Virtual Switch on the FPGA, it can cut the latency on the virtual switch in half, boost the throughput by 3.2X, and crank up the number of VMs hosted on a machine by 2X compared to just running Open Virtual Switch on the Xeon portion of this hybrid chip. That makes a pretty good case for having the FPGA right close to the CPU – provided this chip doesn’t cost too much.</i>

On a whole different level, if you are merely interested in FPGAs in your computer then the PicoEVB neatly goes in the same M.2 slot as wifi cards do and communicates over PCIe, even if just PCIe Gen 2 x1. As far as I am aware this is, by far, the cheapest way to get an FPGA on the PCIe bus.

Note that this is a ~$2500 processor with a ~$5000 FPGA stuck to it.

Depending on the price, this will be interesting for I&#x2F;do-something&#x2F;O workloads like video encoding&#x2F;decoding. Depending on the price, looking forward to it. Of course, depending on the price. :)

Could this be a hint at Intel&#x27;s supercomputing and AI strategy? They cannot compete with GPUs on flops with Xeon, but an embedded FPGA might get them closer.<p>It is a risky strategy however. Even if they can attain similar performance, which I doubt, programmability remains the big problem for FPGAs. I know Intel is pushing openCL but it simply does not have an ecosystem for software right now, and it remains to be seen if they can even enable much of the feature set of openCL on an FPGA.

This is great! I think that some time in the future, FPGA will be a vital part for data processing.<p>In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body).<p>What I am worried about is the infrastructure that is needed to make this happen: Is there even support for this in our compilers? What would support look like?

I thought FPGAs were limited to either cases where you need some custom hardware _now_ or where demand is low because, if demand is high enough and you can wait, custom ASICs are cheaper, lower power, and faster.<p>What has changed here? Are FPGAs faster now or are many more people experimenting, creating sufficient demand for custom hardware at short notice?

This is cool! I have so many questions, like how does it work with context switching? How do they protect access to the cache?

does it mean that you can load your designs on that fpga ? where can we find what features are exposed to sw ?

Looks like a future AWS instance type.