I've always been <i>fascinated</i> by asynchronous hardware design.<p>When you first learn about H/W design in Verilog or VHDL, it feels like your mind is immediately shoehorned and molded by both the literature and your teachers into thinking synchronously (everything has to be clocked, and signals crossing clock domain boundaries are to be treated like they're some form electronic nitroglycerin).<p>As a matter of fact, HDL courses often go without so much as a mention of the possibility of asynchronous design, or if they mention it, it's to say something along the lines of "just don't".<p>It almost feels like designing things asynchronously is a sin to be avoided at all cost.<p>Even further, the synthesis tools themselves will yell at you when you try to do things asynchronously (probably because many of the optimization that can be done with a clocked design don't work).<p>Granted: asynchronous design is harder and bug-prone, but - at least to someone like myself with more of a software engineering background - it also feels a lot more natural than being forced into the straight jacket of clocks.<p>This all leads to the unfortunate situation that while there's been a lot written about how to design with clocks, I haven't come across much literature about asynchronous design <i>methodologies</i>.<p>If anyone on HN has a a reference on asynchronous hardware design methodologies, I'd love to dive into that.