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Porting SBCL to the RISC-V

133 点作者 pome将近 7 年前

4 条评论

brucehoult将近 7 年前
If there is any assembly-language programming needed, or a code generator, then I suggest you start with the code for MIPSle. Many of the instructions and mnemonics are the same.<p>The biggest differences are immediate arithmetic and load&#x2F;store offsets are 12 bit on RISC-V vs 16-bit on MIPS. To compensate, LUI loads 20 bits on RISC-V vs 16 bits on MIPS. So it&#x27;s only immediates or offsets between +&#x2F;-2K and +&#x2F;-32K that are different.<p>Also RISC-V does compare two registers for ordering and branch in one instruction, which older MIPS can&#x27;t do.
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jepler将近 7 年前
Looks like the disparaging ARM-fronted website about RISC-V might have been <a href="https:&#x2F;&#x2F;riscv-basics.com&#x2F;" rel="nofollow">https:&#x2F;&#x2F;riscv-basics.com&#x2F;</a> which has disappeared down the memory hole. One mention at <a href="http:&#x2F;&#x2F;www.osnews.com&#x2F;comments&#x2F;30562" rel="nofollow">http:&#x2F;&#x2F;www.osnews.com&#x2F;comments&#x2F;30562</a> sheds a bit of light.<p>edited to add: here&#x27;s HN&#x27;s discussion at the time: <a href="https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=17489504" rel="nofollow">https:&#x2F;&#x2F;news.ycombinator.com&#x2F;item?id=17489504</a>
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dang将近 7 年前
We changed the url changed from <a href="http:&#x2F;&#x2F;christophe.rhodes.io&#x2F;notes&#x2F;tag&#x2F;riscv&#x2F;" rel="nofollow">http:&#x2F;&#x2F;christophe.rhodes.io&#x2F;notes&#x2F;tag&#x2F;riscv&#x2F;</a> to the introductory article in the series. The other article listed there is <a href="http:&#x2F;&#x2F;christophe.rhodes.io&#x2F;notes&#x2F;blog&#x2F;posts&#x2F;2018&#x2F;first_riscy_steps&#x2F;" rel="nofollow">http:&#x2F;&#x2F;christophe.rhodes.io&#x2F;notes&#x2F;blog&#x2F;posts&#x2F;2018&#x2F;first_risc...</a>.
Annatar将近 7 年前
This has got to be the first processor for which the software is available before a complete computer exists; RISC-V 19” rack mountable servers remain distant science fiction.
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