Intel Unveils a Groundbreaking Way to Make 3D Chips

Engaget has an annoying cookiewall, could we have literally any other article based on the same press release please? (Or ideally the underlying PR)<p><a href="https:&#x2F;&#x2F;hothardware.com&#x2F;news&#x2F;intel-foveros-to-usher-in-industry-first-3d-stacked-system-on-a-chip-designs" rel="nofollow">https:&#x2F;&#x2F;hothardware.com&#x2F;news&#x2F;intel-foveros-to-usher-in-indus...</a><p><a href="https:&#x2F;&#x2F;arstechnica.com&#x2F;gadgets&#x2F;2018&#x2F;12&#x2F;intel-introduces-foveros-3d-die-stacking-for-more-than-just-memory&#x2F;" rel="nofollow">https:&#x2F;&#x2F;arstechnica.com&#x2F;gadgets&#x2F;2018&#x2F;12&#x2F;intel-introduces-fov...</a><p>(maybe underlying PR?) <a href="https:&#x2F;&#x2F;newsroom.intel.com&#x2F;articles&#x2F;new-intel-architectures-technologies-target-expanded-market-opportunities&#x2F;" rel="nofollow">https:&#x2F;&#x2F;newsroom.intel.com&#x2F;articles&#x2F;new-intel-architectures-...</a><p>Responding to the actual technology, the key is what they call &quot;Foveros&quot; or &quot;active interposer&quot;. Previously chips were limited to having interconnect on one side: the traditional solder bumps. It appears that not only do they have through-silicon vias working but they have combined this with having logic on the die - typically this is a problem because the more complex the logic is, the less flat the active side is. The actual layer thickness will vary across layers and across the die by tiny amounts.<p>This is basically the silicon version of mezzanine PCBs: you can stack a fully-capable logic chip directly on top of another chip, usually for handling the IO. The example then also has some DRAM stuck on top with standard package stacking technology like the Raspberry Pi.

I work for Intel on a team that partners w&#x2F; design and manufacturing to build DFX features and tooling. It&#x27;s been quite the ride to enable DFX for Foveros but it&#x27;s really exciting technology.<p>At the end of the day I look at it like this: it&#x27;s getting harder and more expensive to reduce nano-meter size, getting high yields on 5nm, 3nm and beyond is going to be a multi-billion dollar effort for everyone in the industry, with Foveros we can really squeeze water from a rock and build products on advance node tech even if overall yield isn&#x27;t the greatest.<p>I don&#x27;t think it&#x27;s a shock to say that the 18 month window described by Moore&#x27;s Law is probably well behind us. But new innovations like Foveros give me confidence that we still have a long road ahead of us to improve silicon performance.

In undergrad and a little bit into grad school, I did some 3DIC research. It was interesting stuff and really exciting to expand architectural design into 3 dimensions.<p>The biggest problem was heat as the additional layers trap heat in the chip and make it much easier to let the magic smoke out.<p>I don&#x27;t see much in this article explaining any groundbreaking approaches and the diagrams offered look much the same as they did 5 years ago.

I don&#x27;t believe anything Intel says in a press report until I see the actual product. We have been lied to and mislead too many times.

Sounds like one of several backup plans to make decently powerful CPUs next year despite dropping the ball on the 10nm process; it&#x27;s probably mature technology, slightly anticipated from its planned debut (did you notice the slides mentioning the 10nm process?).<p>In sadly related news, the presentation of &quot;Sunny Cove&quot; CPUs (which might or might not use these packaging techniques) mentions the 14nm process but not the 10nm or 7nm ones, brazenly proclaims an &quot;age of architecture&quot;, lists boring incremental improvements and doesn&#x27;t even try to discuss performance, core count or power efficiency.

Chips already get to 100 degrees Celsius with just one layer of transistors: how does thermal dissipation work when you&#x27;re stacking &#x27;chiplets&#x27; on top of each other?

&gt; It&#x27;s developed the first 3D chip architecture that allows logic chips -- things like the CPU and graphics -- to be stacked together.<p>So, they just have a theoretical architecture, is that it ?

What is the difference between this and multi-die stacking? NAND memory packages typically have up to 4 (8?) dies stacked together. Is this something beyond that?

Hah, that&#x27;s a good name. It means &quot;terrifying&quot; in Greek.